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Re: [PATCH v2 10/19] ppc/pnv: Add a big-core mode that joins two regular
From: |
Nicholas Piggin |
Subject: |
Re: [PATCH v2 10/19] ppc/pnv: Add a big-core mode that joins two regular cores |
Date: |
Mon, 15 Jul 2024 16:31:17 +1000 |
On Sat Jul 13, 2024 at 5:19 PM AEST, Cédric Le Goater wrote:
> On 7/12/24 14:02, Nicholas Piggin wrote:
> > POWER9 and POWER10 machines come in two variants, big-core and
> > small-core. Big-core machines are SMT8 from software's point of view,
> > but the low level platform topology ("xscom registers and pervasive
> > addressing"), these look more like a pair of small cores ganged
> > together.
> >
> > Presently the way this is modelled is to create one SMT8 PnvCore and add
> > special cases to xscom and pervasive for big-core mode that tries to
> > split this into two small cores, but this is becoming too complicated to
> > manage.
> >
> > A better approach is to create 2 core structures and ganging them
> > together to look like an SMT8 core in TCG. Then the xscom and pervasive
> > models mostly do not need to differentiate big and small core modes.
> >
> > This change adds initial mode bits and QEMU topology handling to
> > split SMT8 cores into 2xSMT4 cores.
> >
> > Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>
>
> Looks good. See some proposal below,
[snip]
All make sense, thank you will do.
Thnaks,
Nick
- [PATCH v2 03/19] ppc/pnv: Move timebase state into PnvCore, (continued)
- [PATCH v2 03/19] ppc/pnv: Move timebase state into PnvCore, Nicholas Piggin, 2024/07/12
- [PATCH v2 06/19] ppc/pnv: Extend chip_pir class method to TIR as well, Nicholas Piggin, 2024/07/12
- [PATCH v2 07/19] ppc: Add a core_index to CPUPPCState for SMT vCPUs, Nicholas Piggin, 2024/07/12
- [PATCH v2 08/19] target/ppc: Add helpers to check for SMT sibling threads, Nicholas Piggin, 2024/07/12
- [PATCH v2 09/19] ppc: Add has_smt_siblings property to CPUPPCState, Nicholas Piggin, 2024/07/12
- [PATCH v2 11/19] ppc/pnv: Add allow for big-core differences in DT generation, Nicholas Piggin, 2024/07/12
- [PATCH v2 10/19] ppc/pnv: Add a big-core mode that joins two regular cores, Nicholas Piggin, 2024/07/12
- [PATCH v2 12/19] ppc/pnv: Implement big-core PVR for Power9/10, Nicholas Piggin, 2024/07/12
- [PATCH v2 13/19] ppc/pnv: Implement Power9 CPU core thread state indirect register, Nicholas Piggin, 2024/07/12
- [PATCH v2 15/19] ppc/pnv: Add big-core machine property, Nicholas Piggin, 2024/07/12
- [PATCH v2 16/19] system/cpus: Add cpu_pause() function, Nicholas Piggin, 2024/07/12
- [PATCH v2 14/19] ppc/pnv: Add POWER10 ChipTOD quirk for big-core, Nicholas Piggin, 2024/07/12