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[PATCH v5 01/18] hw/arm/smmu-common: Add missing size check for stage-1
From: |
Mostafa Saleh |
Subject: |
[PATCH v5 01/18] hw/arm/smmu-common: Add missing size check for stage-1 |
Date: |
Mon, 15 Jul 2024 08:45:01 +0000 |
According to the SMMU architecture specification (ARM IHI 0070 F.b),
in “3.4 Address sizes”
The address output from the translation causes a stage 1 Address Size
fault if it exceeds the range of the effective IPA size for the given CD.
However, this check was missing.
There is already a similar check for stage-2 against effective PA.
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
hw/arm/smmu-common.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index 1ce706bf94..eb2356bc35 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -381,6 +381,16 @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg,
goto error;
}
+ /*
+ * The address output from the translation causes a stage 1 Address
+ * Size fault if it exceeds the range of the effective IPA size for
+ * the given CD.
+ */
+ if (gpa >= (1ULL << cfg->oas)) {
+ info->type = SMMU_PTW_ERR_ADDR_SIZE;
+ goto error;
+ }
+
tlbe->entry.translated_addr = gpa;
tlbe->entry.iova = iova & ~mask;
tlbe->entry.addr_mask = mask;
--
2.45.2.993.g49e7a77208-goog
- [PATCH v5 00/18] SMMUv3 nested translation support, Mostafa Saleh, 2024/07/15
- [PATCH v5 04/18] hw/arm/smmu: Use enum for SMMU stage, Mostafa Saleh, 2024/07/15
- [PATCH v5 05/18] hw/arm/smmu: Split smmuv3_translate(), Mostafa Saleh, 2024/07/15
- [PATCH v5 06/18] hw/arm/smmu: Consolidate ASID and VMID types, Mostafa Saleh, 2024/07/15
- [PATCH v5 07/18] hw/arm/smmu: Introduce CACHED_ENTRY_TO_ADDR, Mostafa Saleh, 2024/07/15
- [PATCH v5 08/18] hw/arm/smmuv3: Translate CD and TT using stage-2 table, Mostafa Saleh, 2024/07/15