Re: [PATCH v3 19/19] ppc/pnv: Add an LPAR per core machine option

qemu-devel

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v3 19/19] ppc/pnv: Add an LPAR per core machine option

From:	Cédric Le Goater
Subject:	Re: [PATCH v3 19/19] ppc/pnv: Add an LPAR per core machine option
Date:	Tue, 16 Jul 2024 18:52:38 +0200
User-agent:	Mozilla Thunderbird

On 7/16/24 18:26, Nicholas Piggin wrote:

Recent POWER CPUs can operate in "LPAR per core" or "LPAR per thread"
modes. In per-core mode, some SPRs and IPI doorbells are shared between
threads in a core. In per-thread mode, supervisor and user state is
not shared between threads.

OpenPOWER systems after POWER8 use LPAR per thread mode, and it is
required for KVM. Enterprise systems use LPAR per core mode, as they
partition the machine by core.

Implement a lpar-per-core machine option for powernv machines. This
is fixed true for POWER8 machines, and defaults off for P9 and P10.

With this change, powernv8 SMT now works sufficiently to run Linux,
with a single socket. Multi-threaded KVM guests still have problems,
as does multi-socket Linux boot.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>



Reviewed-by: Cédric Le Goater <clg@redhat.com>

Thanks,

C.

---
  include/hw/ppc/pnv.h      |  2 ++
  include/hw/ppc/pnv_chip.h |  1 +
  include/hw/ppc/pnv_core.h |  1 +
  hw/ppc/pnv.c              | 38 ++++++++++++++++++++++++++++++++++++++
  hw/ppc/pnv_core.c         |  8 ++++++++
  target/ppc/cpu_init.c     |  3 ++-
  6 files changed, 52 insertions(+), 1 deletion(-)

diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index b7858d310d..fcb6699150 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -77,6 +77,7 @@ struct PnvMachineClass {
      const char *compat;
      int compat_size;
      int max_smt_threads;
+    bool has_lpar_per_thread;
      bool quirk_tb_big_core;

void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);

@@ -104,6 +105,7 @@ struct PnvMachineState {
      hwaddr       fw_load_addr;

bool big_core;

+    bool         lpar_per_core;
  };

PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id);

diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index 69d8273efe..ee1649babc 100644
--- a/include/hw/ppc/pnv_chip.h
+++ b/include/hw/ppc/pnv_chip.h
@@ -28,6 +28,7 @@ struct PnvChip {
      uint64_t     ram_size;

bool big_core;

+    bool         lpar_per_core;
      uint32_t     nr_cores;
      uint32_t     nr_threads;
      uint64_t     cores_mask;
diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
index 1de79a818e..d8afb4f95f 100644
--- a/include/hw/ppc/pnv_core.h
+++ b/include/hw/ppc/pnv_core.h
@@ -57,6 +57,7 @@ struct PnvCore {
      /*< public >*/
      PowerPCCPU **threads;
      bool big_core;
+    bool lpar_per_core;
      uint32_t pir;
      uint32_t hwid;
      uint64_t hrmor;
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index f7580947ed..8d24fc2a45 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1026,6 +1026,11 @@ static void pnv_init(MachineState *machine)
          exit(1);
      }

+ /* Set lpar-per-core mode if lpar-per-thread is not supported */

+    if (!pmc->has_lpar_per_thread) {
+        pnv->lpar_per_core = true;
+    }
+
      pnv->num_chips =
          machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);

@@ -1102,6 +1107,8 @@ static void pnv_init(MachineState *machine)

                                  &error_fatal);
          object_property_set_bool(chip, "big-core", pnv->big_core,
                                  &error_fatal);
+        object_property_set_bool(chip, "lpar-per-core", pnv->lpar_per_core,
+                                &error_fatal);
          /*
           * The POWER8 machine use the XICS interrupt interface.
           * Propagate the XICS fabric to the chip and its controllers.
@@ -2338,6 +2345,8 @@ static void pnv_chip_core_realize(PnvChip *chip, Error 
**errp)
                                  &error_fatal);
          object_property_set_bool(OBJECT(pnv_core), "quirk-tb-big-core",
                                  pmc->quirk_tb_big_core, &error_fatal);
+        object_property_set_bool(OBJECT(pnv_core), "lpar-per-core",
+                                chip->lpar_per_core, &error_fatal);
          object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip),
                                   &error_abort);

@@ -2373,6 +2382,7 @@ static Property pnv_chip_properties[] = {

      DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
      DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
      DEFINE_PROP_BOOL("big-core", PnvChip, big_core, false),
+    DEFINE_PROP_BOOL("lpar-per-core", PnvChip, lpar_per_core, false),
      DEFINE_PROP_END_OF_LIST(),
  };

@@ -2593,6 +2603,18 @@ static void pnv_machine_set_big_core(Object *obj, bool value, Error **errp)

      pnv->big_core = value;
  }

+static bool pnv_machine_get_lpar_per_core(Object *obj, Error **errp)

+{
+    PnvMachineState *pnv = PNV_MACHINE(obj);
+    return pnv->lpar_per_core;
+}
+
+static void pnv_machine_set_lpar_per_core(Object *obj, bool value, Error 
**errp)
+{
+    PnvMachineState *pnv = PNV_MACHINE(obj);
+    pnv->lpar_per_core = value;
+}
+
  static bool pnv_machine_get_hb(Object *obj, Error **errp)
  {
      PnvMachineState *pnv = PNV_MACHINE(obj);
@@ -2632,6 +2654,8 @@ static void pnv_machine_power8_class_init(ObjectClass 
*oc, void *data)
      pmc->compat = compat;
      pmc->compat_size = sizeof(compat);
      pmc->max_smt_threads = 8;
+    /* POWER8 is always lpar-per-core mode */
+    pmc->has_lpar_per_thread = false;

machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);

  }
@@ -2657,6 +2681,7 @@ static void pnv_machine_power9_class_init(ObjectClass 
*oc, void *data)
      pmc->compat = compat;
      pmc->compat_size = sizeof(compat);
      pmc->max_smt_threads = 4;
+    pmc->has_lpar_per_thread = true;
      pmc->dt_power_mgt = pnv_dt_power_mgt;

machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);

@@ -2666,6 +2691,12 @@ static void pnv_machine_power9_class_init(ObjectClass 
*oc, void *data)
                                     pnv_machine_set_big_core);
      object_class_property_set_description(oc, "big-core",
                                "Use big-core (aka fused-core) mode");
+
+    object_class_property_add_bool(oc, "lpar-per-core",
+                                   pnv_machine_get_lpar_per_core,
+                                   pnv_machine_set_lpar_per_core);
+    object_class_property_set_description(oc, "lpar-per-core",
+                              "Use 1 LPAR per core mode");
  }

static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data)

@@ -2688,6 +2719,7 @@ static void pnv_machine_p10_common_class_init(ObjectClass 
*oc, void *data)
      pmc->compat = compat;
      pmc->compat_size = sizeof(compat);
      pmc->max_smt_threads = 4;
+    pmc->has_lpar_per_thread = true;
      pmc->quirk_tb_big_core = true;
      pmc->dt_power_mgt = pnv_dt_power_mgt;

@@ -2713,6 +2745,12 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)

                                     pnv_machine_set_big_core);
      object_class_property_set_description(oc, "big-core",
                                "Use big-core (aka fused-core) mode");
+
+    object_class_property_add_bool(oc, "lpar-per-core",
+                                   pnv_machine_get_lpar_per_core,
+                                   pnv_machine_set_lpar_per_core);
+    object_class_property_set_description(oc, "lpar-per-core",
+                              "Use 1 LPAR per core mode");
  }

static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data)

diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 8ed1cfe8a2..0384122054 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -208,6 +208,9 @@ static uint64_t pnv_core_power10_xscom_read(void *opaque, 
hwaddr addr,
                  val |= PPC_BIT(56 + i);
              }
          }
+        if (pc->lpar_per_core) {
+            val |= PPC_BIT(62);
+        }
          break;
      case PNV10_XSCOM_EC_CORE_THREAD_INFO:
          break;
@@ -321,6 +324,10 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU 
*cpu, Error **errp,
          env->core_index = core_hwid;
      }

+ if (pc->lpar_per_core) {

+        cpu_ppc_set_1lpar(cpu);
+    }
+
      /* Set time-base frequency to 512 MHz */
      cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
  }
@@ -427,6 +434,7 @@ static Property pnv_core_properties[] = {
      DEFINE_PROP_BOOL("big-core", PnvCore, big_core, false),
      DEFINE_PROP_BOOL("quirk-tb-big-core", PnvCore, tod_state.big_core_quirk,
                       false),
+    DEFINE_PROP_BOOL("lpar-per-core", PnvCore, lpar_per_core, false),
      DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *),
      DEFINE_PROP_END_OF_LIST(),
  };
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 81dd4e1a7a..4ba7f54510 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6803,7 +6803,8 @@ void cpu_ppc_set_1lpar(PowerPCCPU *cpu)

/*

       * pseries SMT means "LPAR per core" mode, e.g., msgsndp is usable
-     * between threads.
+     * between threads. powernv be in either mode, and it mostly affects
+     * supervisor visible registers and instructions.
       */
      if (env->flags & POWERPC_FLAG_SMT) {
          env->flags |= POWERPC_FLAG_SMT_1LPAR;

[Prev in Thread]

Current Thread

[Next in Thread]

[PATCH v3 04/19] target/ppc: Move SPR indirect registers into PnvCore, (continued)
- [PATCH v3 04/19] target/ppc: Move SPR indirect registers into PnvCore, Nicholas Piggin, 2024/07/16
- [PATCH v3 08/19] target/ppc: Add helpers to check for SMT sibling threads, Nicholas Piggin, 2024/07/16
- [PATCH v3 13/19] ppc/pnv: Implement Power9 CPU core thread state indirect register, Nicholas Piggin, 2024/07/16
  - Re: [PATCH v3 13/19] ppc/pnv: Implement Power9 CPU core thread state indirect register, Cédric Le Goater, 2024/07/16
- [PATCH v3 10/19] ppc/pnv: Add a big-core mode that joins two regular cores, Nicholas Piggin, 2024/07/16
- [PATCH v3 14/19] ppc/pnv: Add POWER10 ChipTOD quirk for big-core, Nicholas Piggin, 2024/07/16
  - Re: [PATCH v3 14/19] ppc/pnv: Add POWER10 ChipTOD quirk for big-core, Cédric Le Goater, 2024/07/16
- [PATCH v3 15/19] ppc/pnv: Add big-core machine property, Nicholas Piggin, 2024/07/16
  - Re: [PATCH v3 15/19] ppc/pnv: Add big-core machine property, Cédric Le Goater, 2024/07/16
- [PATCH v3 19/19] ppc/pnv: Add an LPAR per core machine option, Nicholas Piggin, 2024/07/16
  - Re: [PATCH v3 19/19] ppc/pnv: Add an LPAR per core machine option, Cédric Le Goater <=
- [PATCH v3 06/19] ppc/pnv: Extend chip_pir class method to TIR as well, Nicholas Piggin, 2024/07/16
- [PATCH v3 09/19] ppc: Add has_smt_siblings property to CPUPPCState, Nicholas Piggin, 2024/07/16
- [PATCH v3 11/19] ppc/pnv: Add allow for big-core differences in DT generation, Nicholas Piggin, 2024/07/16
  - Re: [PATCH v3 11/19] ppc/pnv: Add allow for big-core differences in DT generation, Cédric Le Goater, 2024/07/16
- [PATCH v3 07/19] ppc: Add a core_index to CPUPPCState for SMT vCPUs, Nicholas Piggin, 2024/07/16
- [PATCH v3 16/19] system/cpus: Add cpu_pause() function, Nicholas Piggin, 2024/07/16
- [PATCH v3 17/19] ppc/pnv: Add a CPU nmi and resume function, Nicholas Piggin, 2024/07/16
- [PATCH v3 18/19] ppc/pnv: Implement POWER10 PC xscom registers for direct controls, Nicholas Piggin, 2024/07/16

Prev by Date: Re: [PATCH v3 15/19] ppc/pnv: Add big-core machine property
Next by Date: Re: [PATCH v3 13/19] ppc/pnv: Implement Power9 CPU core thread state indirect register
Previous by thread: [PATCH v3 19/19] ppc/pnv: Add an LPAR per core machine option
Next by thread: [PATCH v3 06/19] ppc/pnv: Extend chip_pir class method to TIR as well
Index(es):
- Date
- Thread