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Re: [PATCH v5 16/18] hw/arm/smmuv3: Handle translation faults according
From: |
Eric Auger |
Subject: |
Re: [PATCH v5 16/18] hw/arm/smmuv3: Handle translation faults according to SMMUPTWEventInfo |
Date: |
Wed, 17 Jul 2024 17:31:21 +0200 |
User-agent: |
Mozilla Thunderbird |
On 7/15/24 10:45, Mostafa Saleh wrote:
> Previously, to check if faults are enabled, it was sufficient to check
> the current stage of translation and check the corresponding
> record_faults flag.
>
> However, with nesting, it is possible for stage-1 (nested) translation
> to trigger a stage-2 fault, so we check SMMUPTWEventInfo as it would
> have the correct stage set from the page table walk.
>
> Signed-off-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Eric
> ---
> hw/arm/smmuv3.c | 15 ++++++++-------
> 1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
> index 84cd314b33..d052a2ba24 100644
> --- a/hw/arm/smmuv3.c
> +++ b/hw/arm/smmuv3.c
> @@ -34,9 +34,10 @@
> #include "smmuv3-internal.h"
> #include "smmu-internal.h"
>
> -#define PTW_RECORD_FAULT(cfg) (((cfg)->stage == SMMU_STAGE_1) ? \
> - (cfg)->record_faults : \
> - (cfg)->s2cfg.record_faults)
> +#define PTW_RECORD_FAULT(ptw_info, cfg) (((ptw_info).stage == SMMU_STAGE_1
> && \
> + (cfg)->record_faults) || \
> + ((ptw_info).stage == SMMU_STAGE_2 &&
> \
> + (cfg)->s2cfg.record_faults))
>
> /**
> * smmuv3_trigger_irq - pulse @irq if enabled and update
> @@ -933,7 +934,7 @@ static SMMUTranslationStatus
> smmuv3_do_translate(SMMUv3State *s, hwaddr addr,
> event->u.f_walk_eabt.addr2 = ptw_info.addr;
> break;
> case SMMU_PTW_ERR_TRANSLATION:
> - if (PTW_RECORD_FAULT(cfg)) {
> + if (PTW_RECORD_FAULT(ptw_info, cfg)) {
> event->type = SMMU_EVT_F_TRANSLATION;
> event->u.f_translation.addr2 = ptw_info.addr;
> event->u.f_translation.class = class;
> @@ -941,7 +942,7 @@ static SMMUTranslationStatus
> smmuv3_do_translate(SMMUv3State *s, hwaddr addr,
> }
> break;
> case SMMU_PTW_ERR_ADDR_SIZE:
> - if (PTW_RECORD_FAULT(cfg)) {
> + if (PTW_RECORD_FAULT(ptw_info, cfg)) {
> event->type = SMMU_EVT_F_ADDR_SIZE;
> event->u.f_addr_size.addr2 = ptw_info.addr;
> event->u.f_addr_size.class = class;
> @@ -949,7 +950,7 @@ static SMMUTranslationStatus
> smmuv3_do_translate(SMMUv3State *s, hwaddr addr,
> }
> break;
> case SMMU_PTW_ERR_ACCESS:
> - if (PTW_RECORD_FAULT(cfg)) {
> + if (PTW_RECORD_FAULT(ptw_info, cfg)) {
> event->type = SMMU_EVT_F_ACCESS;
> event->u.f_access.addr2 = ptw_info.addr;
> event->u.f_access.class = class;
> @@ -957,7 +958,7 @@ static SMMUTranslationStatus
> smmuv3_do_translate(SMMUv3State *s, hwaddr addr,
> }
> break;
> case SMMU_PTW_ERR_PERMISSION:
> - if (PTW_RECORD_FAULT(cfg)) {
> + if (PTW_RECORD_FAULT(ptw_info, cfg)) {
> event->type = SMMU_EVT_F_PERMISSION;
> event->u.f_permission.addr2 = ptw_info.addr;
> event->u.f_permission.class = class;
- [PATCH v5 08/18] hw/arm/smmuv3: Translate CD and TT using stage-2 table, (continued)
- [PATCH v5 08/18] hw/arm/smmuv3: Translate CD and TT using stage-2 table, Mostafa Saleh, 2024/07/15
- [PATCH v5 09/18] hw/arm/smmu-common: Rework TLB lookup for nesting, Mostafa Saleh, 2024/07/15
- [PATCH v5 11/18] hw/arm/smmu-common: Support nested translation, Mostafa Saleh, 2024/07/15
- [PATCH v5 10/18] hw/arm/smmu-common: Add support for nested TLB, Mostafa Saleh, 2024/07/15
- [PATCH v5 13/18] hw/arm/smmu: Introduce smmu_iotlb_inv_asid_vmid, Mostafa Saleh, 2024/07/15
- [PATCH v5 12/18] hw/arm/smmu: Support nesting in smmuv3_range_inval(), Mostafa Saleh, 2024/07/15
- [PATCH v5 16/18] hw/arm/smmuv3: Handle translation faults according to SMMUPTWEventInfo, Mostafa Saleh, 2024/07/15
- Re: [PATCH v5 16/18] hw/arm/smmuv3: Handle translation faults according to SMMUPTWEventInfo,
Eric Auger <=
- [PATCH v5 14/18] hw/arm/smmu: Support nesting in the rest of commands, Mostafa Saleh, 2024/07/15
- [PATCH v5 17/18] hw/arm/smmuv3: Support and advertise nesting, Mostafa Saleh, 2024/07/15
- [PATCH v5 15/18] hw/arm/smmuv3: Support nested SMMUs in smmuv3_notify_iova(), Mostafa Saleh, 2024/07/15
- [PATCH v5 18/18] hw/arm/smmu: Refactor SMMU OAS, Mostafa Saleh, 2024/07/15
- Re: [PATCH v5 00/18] SMMUv3 nested translation support, Jean-Philippe Brucker, 2024/07/17