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RE: [PATCH v2] pci-bridge: avoid linking a single downstream port more t
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From: |
Xingtao Yao (Fujitsu) |
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Subject: |
RE: [PATCH v2] pci-bridge: avoid linking a single downstream port more than once |
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Date: |
Thu, 18 Jul 2024 01:09:57 +0000 |
> -----Original Message-----
> From: Michael S. Tsirkin <mst@redhat.com>
> Sent: Wednesday, July 17, 2024 8:04 PM
> To: Yao, Xingtao/姚 幸涛 <yaoxt.fnst@fujitsu.com>
> Cc: marcel.apfelbaum@gmail.com; qemu-devel@nongnu.org;
> jonathan.cameron@huawei.com
> Subject: Re: [PATCH v2] pci-bridge: avoid linking a single downstream port
> more
> than once
>
> On Wed, Jul 17, 2024 at 04:56:21AM -0400, Yao Xingtao wrote:
> > Since the downstream port is not checked, two slots can be linked to
> > a single port. However, this can prevent the driver from detecting the
> > device properly.
> >
> > It is necessary to ensure that a downstream port is not linked more than
> > once.
> >
> > Links:
> https://lore.kernel.org/qemu-devel/OSZPR01MB6453BC61D2FF4035F18084EF8D
> DC2@OSZPR01MB6453.jpnprd01.prod.outlook.com
> > Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
>
> You also need to take ARI into account.
> That can look like slot != 0.
Sorry, I'm not familiar with the PCIe protocol, could you explain it in detail?