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Re: [PATCH v6 7/8] target/riscv: Add any32 and max32 CPU for RV64 QEMU
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From: |
Peter Maydell |
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Subject: |
Re: [PATCH v6 7/8] target/riscv: Add any32 and max32 CPU for RV64 QEMU |
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Date: |
Wed, 24 Jul 2024 19:22:24 +0100 |
On Sat, 20 Jul 2024 at 00:18, LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
> We may need 32-bit max or 32-bit any CPU for RV64 QEMU. Thus we add
> these two CPUs for RV64 QEMU.
>
> The reason we don't expose them to RV32 QEMU is that we already have
> max or any cpu with the same configuration. Another reason is that
> we want to follow the RISC-V custom where addw instruction doesn't
> exist in RV32 CPU.
You might want to consider whether you'd rather have this be
"-cpu max,64=off" (replace "64" with whatever feature name the
architecture uses for 64-bit support). That's the way I would plan
to handle it for Arm (with "-cpu max,aarch64=off"; that works for
KVM right now and if we ever wanted to handle it for TCG would be how
I'd want the command line syntax to go).
-- PMM
- [PATCH v6 1/8] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI, (continued)
- [PATCH v6 1/8] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI, LIU Zhiwei, 2024/07/19
- [PATCH v6 2/8] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32, LIU Zhiwei, 2024/07/19
- [PATCH v6 3/8] target/riscv: Correct SXL return value for RV32 in RV64 QEMU, LIU Zhiwei, 2024/07/19
- [PATCH v6 4/8] target/riscv: Detect sxl to set bit width for RV32 in RV64, LIU Zhiwei, 2024/07/19
- [PATCH v6 5/8] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU, LIU Zhiwei, 2024/07/19
- [PATCH v6 6/8] target/riscv: Enable RV32 CPU support in RV64 QEMU, LIU Zhiwei, 2024/07/19
- [PATCH v6 7/8] target/riscv: Add any32 and max32 CPU for RV64 QEMU, LIU Zhiwei, 2024/07/19
- [PATCH v6 8/8] tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU, LIU Zhiwei, 2024/07/19
- Re: [PATCH v6 0/8] target/riscv: Expose RV32 cpu to RV64 QEMU, Alistair Francis, 2024/07/23