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[PULL 12/21] target/arm: Don't assert for 128-bit tile accesses when SVL
From: |
Peter Maydell |
Subject: |
[PULL 12/21] target/arm: Don't assert for 128-bit tile accesses when SVL is 128 |
Date: |
Tue, 30 Jul 2024 10:40:11 +0100 |
For an instruction which accesses a 128-bit element tile when
the SVL is also 128 (for example MOV z0.Q, p0/M, ZA0H.Q[w0,0]),
we will assert in get_tile_rowcol():
qemu-system-aarch64: ../../tcg/tcg-op.c:926: tcg_gen_deposit_z_i32: Assertion
`len > 0' failed.
This happens because we calculate
len = ctz32(streaming_vec_reg_size(s)) - esz;$
but if the SVL and the element size are the same len is 0, and
the deposit operation asserts.
In this case the ZA storage contains exactly one 128 bit
element ZA tile, and the horizontal or vertical slice is just
that tile. This means that regardless of the index value in
the Ws register, we always access that tile. (In pseudocode terms,
we calculate (index + offset) MOD 1, which is 0.)
Special case the len == 0 case to avoid hitting the assertion
in tcg_gen_deposit_z_i32().
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240722172957.1041231-2-peter.maydell@linaro.org
---
target/arm/tcg/translate-sme.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
index 185a8a917b0..a50a419af27 100644
--- a/target/arm/tcg/translate-sme.c
+++ b/target/arm/tcg/translate-sme.c
@@ -49,7 +49,15 @@ static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz,
int rs,
/* Prepare a power-of-two modulo via extraction of @len bits. */
len = ctz32(streaming_vec_reg_size(s)) - esz;
- if (vertical) {
+ if (!len) {
+ /*
+ * SVL is 128 and the element size is 128. There is exactly
+ * one 128x128 tile in the ZA storage, and so we calculate
+ * (Rs + imm) MOD 1, which is always 0. We need to special case
+ * this because TCG doesn't allow deposit ops with len 0.
+ */
+ tcg_gen_movi_i32(tmp, 0);
+ } else if (vertical) {
/*
* Compute the byte offset of the index within the tile:
* (index % (svl / size)) * size
--
2.34.1
- [PULL 05/21] hvf: arm: Raise an exception for sysreg by default, (continued)
- [PULL 05/21] hvf: arm: Raise an exception for sysreg by default, Peter Maydell, 2024/07/30
- [PULL 07/21] hvf: arm: Do not advance PC when raising an exception, Peter Maydell, 2024/07/30
- [PULL 15/21] target/arm: Ignore SMCR_EL2.LEN and SVCR_EL2.LEN if EL2 is not enabled, Peter Maydell, 2024/07/30
- [PULL 18/21] target/m68k: avoid shift into sign bit in dump_address_map(), Peter Maydell, 2024/07/30
- [PULL 19/21] target/i386: Remove dead assignment to ss in do_interrupt64(), Peter Maydell, 2024/07/30
- [PULL 20/21] target/sh4: Avoid shift into sign bit in update_itlb_use(), Peter Maydell, 2024/07/30
- [PULL 21/21] system/physmem: Where we assume we have a RAM MR, assert it, Peter Maydell, 2024/07/30
- [PULL 09/21] hw/misc/bcm2835_property: Avoid overflow in OTP access properties, Peter Maydell, 2024/07/30
- [PULL 11/21] hw/misc/bcm2835_property: Reduce scope of variables in mbox push function, Peter Maydell, 2024/07/30
- [PULL 10/21] hw/misc/bcm2835_property: Restrict scope of start_num, number, otp_row, Peter Maydell, 2024/07/30
- [PULL 12/21] target/arm: Don't assert for 128-bit tile accesses when SVL is 128,
Peter Maydell <=
- [PULL 13/21] target/arm: Fix UMOPA/UMOPS of 16-bit values, Peter Maydell, 2024/07/30
- [PULL 16/21] target/tricore: Use unsigned types for bitops in helper_eq_b(), Peter Maydell, 2024/07/30
- [PULL 17/21] target/xtensa: Make use of 'segment' in pptlb helper less confusing, Peter Maydell, 2024/07/30
- Re: [PULL 00/21] target-arm queue, Richard Henderson, 2024/07/30