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[PATCH 03/18] bsd-user: Implement RISC-V CPU register cloning and reset
From: |
Ajeet Singh |
Subject: |
[PATCH 03/18] bsd-user: Implement RISC-V CPU register cloning and reset functions |
Date: |
Fri, 2 Aug 2024 18:34:08 +1000 |
From: Mark Corbin <mark.corbin@embecsom.com>
Added functions for cloning CPU registers and resetting the CPU state
for RISC-V architecture.
Signed-off-by: Mark Corbin <mark.corbin@embecsom.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
---
bsd-user/riscv/target_arch_cpu.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h
index 5b436b2ac9..53db790517 100644
--- a/bsd-user/riscv/target_arch_cpu.h
+++ b/bsd-user/riscv/target_arch_cpu.h
@@ -130,4 +130,18 @@ static inline void target_cpu_loop(CPURISCVState *env)
}
}
+static inline void target_cpu_clone_regs(CPURISCVState *env, target_ulong
newsp)
+{
+ if (newsp) {
+ env->gpr[xSP] = newsp;
+ }
+
+ env->gpr[xA0] = 0; /* a0 */
+ env->gpr[5] = 0; /* t0 */
+}
+
+static inline void target_cpu_reset(CPUArchState *env)
+{
+}
+
#endif /* TARGET_ARCH_CPU_H */
--
2.34.1
- [PATCH 00/18] bsd-user: Comprehensive RISCV support, Ajeet Singh, 2024/08/02
- [PATCH 01/18] bsd-user: Implement RISC-V CPU initialization and main loop, Ajeet Singh, 2024/08/02
- [PATCH 02/18] bsd-user: Add RISC-V CPU execution loop and syscall handling, Ajeet Singh, 2024/08/02
- [PATCH 03/18] bsd-user: Implement RISC-V CPU register cloning and reset functions,
Ajeet Singh <=
- [PATCH 04/18] bsd-user: Implement RISC-V TLS register setup, Ajeet Singh, 2024/08/02
- [PATCH 05/18] bsd-user: Add prototype for RISC-V TLS register setup, Ajeet Singh, 2024/08/02
- [PATCH 06/18] bsd-user: Add RISC-V ELF definitions and hardware capability detection, Ajeet Singh, 2024/08/02
- [PATCH 07/18] bsd-user: Define RISC-V register structures and register copying, Ajeet Singh, 2024/08/02
- [PATCH 08/18] bsd-user: Add RISC-V signal trampoline setup function, Ajeet Singh, 2024/08/02