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Re: [PATCH v2 16/17] intel_iommu: Introduce a property to control FS1GP
From: |
CLEMENT MATHIEU--DRIF |
Subject: |
Re: [PATCH v2 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting |
Date: |
Tue, 6 Aug 2024 06:33:52 +0000 |
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
On 05/08/2024 08:27, Zhenzhong Duan wrote:
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>
>
> When host IOMMU doesn't support FS1GP but vIOMMU does, host IOMMU
> can't translate stage-1 page table from guest correctly.
>
> Add a property x-cap-fs1gp for user to turn FS1GP off so that
> nested page table on host side works.
>
> This property has no effect when vIOMMU isn't in scalable modern
> mode.
>
> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> ---
> include/hw/i386/intel_iommu.h | 1 +
> hw/i386/intel_iommu.c | 5 ++++-
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
> index 650641544c..f6d9b41b80 100644
> --- a/include/hw/i386/intel_iommu.h
> +++ b/include/hw/i386/intel_iommu.h
> @@ -308,6 +308,7 @@ struct IntelIOMMUState {
> bool dma_drain; /* Whether DMA r/w draining enabled */
> bool dma_translation; /* Whether DMA translation supported */
> bool pasid; /* Whether to support PASID */
> + bool fs1gp; /* First Stage 1-GByte Page Support */
>
> /*
> * Protects IOMMU states in general. Currently it protects the
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 9e973bd710..d7e7354db4 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -3778,6 +3778,7 @@ static Property vtd_properties[] = {
> DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, false),
> DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true),
> DEFINE_PROP_BOOL("dma-translation", IntelIOMMUState, dma_translation,
> true),
> + DEFINE_PROP_BOOL("x-cap-fs1gp", IntelIOMMUState, fs1gp, true),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> @@ -4506,7 +4507,9 @@ static void vtd_cap_init(IntelIOMMUState *s)
> /* TODO: read cap/ecap from host to decide which cap to be exposed. */
> if (s->scalable_modern) {
> s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_FLTS;
> - s->cap |= VTD_CAP_FS1GP;
> + if (s->fs1gp) {
> + s->cap |= VTD_CAP_FS1GP;
> + }
> } else if (s->scalable_mode) {
> s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_SLTS;
> }
> --
> 2.34.1
>
- [PATCH v2 12/17] intel_iommu: Add support for PASID-based device IOTLB invalidation, (continued)
- [PATCH v2 12/17] intel_iommu: Add support for PASID-based device IOTLB invalidation, Zhenzhong Duan, 2024/08/05
- [PATCH v2 11/17] intel_iommu: Add an internal API to find an address space with PASID, Zhenzhong Duan, 2024/08/05
- [PATCH v2 15/17] intel_iommu: Modify x-scalable-mode to be string option to expose scalable modern mode, Zhenzhong Duan, 2024/08/05
- [PATCH v2 14/17] intel_iommu: Set default aw_bits to 48 in scalable modren mode, Zhenzhong Duan, 2024/08/05
- [PATCH v2 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting, Zhenzhong Duan, 2024/08/05
- Re: [PATCH v2 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting,
CLEMENT MATHIEU--DRIF <=
- Re: [PATCH v2 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting, Yi Liu, 2024/08/14
- RE: [PATCH v2 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting, Duan, Zhenzhong, 2024/08/14
- Re: [PATCH v2 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting, Yi Liu, 2024/08/19
- RE: [PATCH v2 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting, Duan, Zhenzhong, 2024/08/19
- Re: [PATCH v2 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting, Yi Liu, 2024/08/19
[PATCH v2 17/17] tests/qtest: Add intel-iommu test, Zhenzhong Duan, 2024/08/05