Re: [PATCH 12/17] target/arm: Convert handle_vec_simd_shri to decodetree

[Peter Maydell]

On Wed, 17 Jul 2024 at 07:11, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This includes SSHR, USHR, SSRA, USRA, SRSHR, URSHR, SRSRA, URSRA, SRI.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/tcg/translate-a64.c | 109 +++++++++++++++------------------
>  target/arm/tcg/a64.decode      |  27 +++++++-
>  2 files changed, 74 insertions(+), 62 deletions(-)
>
> diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
> index d0a3450d75..1e482477c5 100644
> --- a/target/arm/tcg/translate-a64.c
> +++ b/target/arm/tcg/translate-a64.c
> @@ -68,6 +68,22 @@ static int scale_by_log2_tag_granule(DisasContext *s, int 
> x)
>      return x << LOG2_TAG_GRANULE;
>  }
>
> +/*
> + * For Advanced SIMD shift by immediate, extract esz from immh.
> + * The result must be validated by the translator: MO_8 <= x <= MO_64.
> + */
> +static int esz_immh(DisasContext *s, int x)
> +{
> +    return 32 - clz32(x) - 1;
> +}
> +
> +/* For Advanced SIMD shift by immediate, right shift count. */
> +static int rcount_immhb(DisasContext *s, int x)
> +{
> +    int size = esz_immh(s, x >> 3);
> +    return (16 << size) - x;

We need to avoid shift-by-negative-value if esz_immh()
returns < 0 here, right? (like commit 76916dfa8 did
for tszimm_esz())

-- PMM