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Re: [PATCH v1 14/15] tcg/riscv: Implement vector roti/v/x shi ops
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH v1 14/15] tcg/riscv: Implement vector roti/v/x shi ops |
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Date: |
Wed, 14 Aug 2024 19:55:37 +1000 |
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User-agent: |
Mozilla Thunderbird |
On 8/13/24 21:34, LIU Zhiwei wrote:
+ case INDEX_op_shli_vec:
+ if (a2 > 31) {
+ t2 = tcg_temp_new_i32();
+ tcg_gen_movi_i32(t2, (int32_t)a2);
+ tcg_gen_shls_vec(vece, v0, v1, t2);
Drop the movi, just pass tcg_constant_i32(a2) as the second source.
+ case INDEX_op_rotls_vec:
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_temp_new_i32();
+ tcg_gen_sub_i32(t2, tcg_constant_i32(8 << vece),
+ temp_tcgv_i32(arg_temp(a2)));
+ tcg_gen_shrs_vec(vece, v0, v1, t2);
Only the low lg2(SEW) bits are used; you can just tcg_gen_neg_i32.
+ case INDEX_op_rotlv_vec:
+ v2 = temp_tcgv_vec(arg_temp(a2));
+ t1 = tcg_temp_new_vec(type);
+ c1 = tcg_constant_vec(type, vece, 8 << vece);
+ tcg_gen_sub_vec(vece, t1, c1, v2);
Likewise tcg_gen_neg_vec.
+ case INDEX_op_rotrv_vec:
+ v2 = temp_tcgv_vec(arg_temp(a2));
+ t1 = tcg_temp_new_vec(type);
+ c1 = tcg_constant_vec(type, vece, 8 << vece);
+ tcg_gen_sub_vec(vece, t1, c1, v2);
Likewise.
r~
- [PATCH v1 09/15] tcg/riscv: Implement vector cmp ops, (continued)
- [PATCH v1 09/15] tcg/riscv: Implement vector cmp ops, LIU Zhiwei, 2024/08/13
- [PATCH v1 10/15] tcg/riscv: Implement vector not/neg ops, LIU Zhiwei, 2024/08/13
- [PATCH v1 11/15] tcg/riscv: Implement vector sat/mul ops, LIU Zhiwei, 2024/08/13
- [PATCH v1 12/15] tcg/riscv: Implement vector min/max ops, LIU Zhiwei, 2024/08/13
- [PATCH v1 13/15] tcg/riscv: Implement vector shs/v ops, LIU Zhiwei, 2024/08/13
- [PATCH v1 14/15] tcg/riscv: Implement vector roti/v/x shi ops, LIU Zhiwei, 2024/08/13
- Re: [PATCH v1 14/15] tcg/riscv: Implement vector roti/v/x shi ops,
Richard Henderson <=
- [PATCH v1 15/15] tcg/riscv: Enable vector TCG host-native, LIU Zhiwei, 2024/08/13