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[PATCH v2 10/17] bsd-user: Define RISC-V VM parameters and helper functi
From: |
Ajeet Singh |
Subject: |
[PATCH v2 10/17] bsd-user: Define RISC-V VM parameters and helper functions |
Date: |
Sat, 17 Aug 2024 03:09:42 +1000 |
From: Mark Corbin <mark@dibsco.co.uk>
Added definitions for RISC-V VM parameters, including maximum and
default sizes for text, data, and stack, as well as address space
limits.
Implemented helper functions for retrieving and setting specific
values in the CPU state, such as stack pointer and return values.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
bsd-user/riscv/target_arch_vmparam.h | 53 ++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
create mode 100644 bsd-user/riscv/target_arch_vmparam.h
diff --git a/bsd-user/riscv/target_arch_vmparam.h
b/bsd-user/riscv/target_arch_vmparam.h
new file mode 100644
index 0000000000..0f2486def1
--- /dev/null
+++ b/bsd-user/riscv/target_arch_vmparam.h
@@ -0,0 +1,53 @@
+/*
+ * RISC-V VM parameters definitions
+ *
+ * Copyright (c) 2019 Mark Corbin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_VMPARAM_H
+#define TARGET_ARCH_VMPARAM_H
+
+#include "cpu.h"
+
+/* Compare with riscv/include/vmparam.h */
+#define TARGET_MAXTSIZ (1 * GiB) /* max text size */
+#define TARGET_DFLDSIZ (128 * MiB) /* initial data size limit */
+#define TARGET_MAXDSIZ (1 * GiB) /* max data size */
+#define TARGET_DFLSSIZ (128 * MiB) /* initial stack size limit */
+#define TARGET_MAXSSIZ (1 * GiB) /* max stack size */
+#define TARGET_SGROWSIZ (128 * KiB) /* amount to grow stack */
+
+#define TARGET_VM_MINUSER_ADDRESS (0x0000000000000000UL)
+#define TARGET_VM_MAXUSER_ADDRESS (0x0000004000000000UL)
+
+#define TARGET_USRSTACK (TARGET_VM_MAXUSER_ADDRESS - TARGET_PAGE_SIZE)
+
+static inline abi_ulong get_sp_from_cpustate(CPURISCVState *state)
+{
+ return state->gpr[xSP];
+}
+
+static inline void set_second_rval(CPURISCVState *state, abi_ulong retval2)
+{
+ state->gpr[xA1] = retval2;
+}
+
+static inline abi_ulong get_second_rval(CPURISCVState *state)
+{
+ return state->gpr[xA1];
+}
+
+#endif /* TARGET_ARCH_VMPARAM_H */
--
2.34.1
- [PATCH v2 07/17] bsd-user: Add RISC-V signal trampoline setup function, (continued)
- [PATCH v2 07/17] bsd-user: Add RISC-V signal trampoline setup function, Ajeet Singh, 2024/08/16
- [PATCH v2 11/17] bsd-user: Define RISC-V system call structures and constants, Ajeet Singh, 2024/08/16
- [PATCH v2 04/17] bsd-user: Implement RISC-V TLS register setup, Ajeet Singh, 2024/08/16
- [PATCH v2 12/17] bsd-user: Add generic RISC-V64 target definitions, Ajeet Singh, 2024/08/16
- [PATCH v2 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection, Ajeet Singh, 2024/08/16
- [PATCH v2 09/17] bsd-user: Add RISC-V thread setup and initialization support, Ajeet Singh, 2024/08/16
- [PATCH v2 06/17] bsd-user: Define RISC-V register structures and register copying, Ajeet Singh, 2024/08/16
- [PATCH v2 08/17] bsd-user: Implement RISC-V sysarch system call emulation, Ajeet Singh, 2024/08/16
- [PATCH v2 10/17] bsd-user: Define RISC-V VM parameters and helper functions,
Ajeet Singh <=
- [PATCH v2 13/17] bsd-user: Define RISC-V signal handling structures and constants, Ajeet Singh, 2024/08/16
- [PATCH v2 14/17] bsd-user: Implement RISC-V signal trampoline setup functions, Ajeet Singh, 2024/08/16
- [PATCH v2 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV, Ajeet Singh, 2024/08/16
- [PATCH v2 15/17] bsd-user: Implement 'get_mcontext' for RISC-V, Ajeet Singh, 2024/08/16
- [PATCH v2 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files, Ajeet Singh, 2024/08/16