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[PATCH v3 07/17] bsd-user: Add RISC-V signal trampoline setup function
From: |
Ajeet Singh |
Subject: |
[PATCH v3 07/17] bsd-user: Add RISC-V signal trampoline setup function |
Date: |
Sat, 24 Aug 2024 14:56:25 +1000 |
From: Mark Corbin <mark@dibsco.co.uk>
Implemented the 'setup_sigtramp' function for setting up the signal
trampoline code in the RISC-V architecture.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
bsd-user/riscv/target_arch_sigtramp.h | 42 +++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
create mode 100644 bsd-user/riscv/target_arch_sigtramp.h
diff --git a/bsd-user/riscv/target_arch_sigtramp.h
b/bsd-user/riscv/target_arch_sigtramp.h
new file mode 100644
index 0000000000..fce673e65a
--- /dev/null
+++ b/bsd-user/riscv/target_arch_sigtramp.h
@@ -0,0 +1,42 @@
+/*
+ * RISC-V sigcode
+ *
+ * Copyright (c) 2019 Mark Corbin
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_SIGTRAMP_H
+#define TARGET_ARCH_SIGTRAMP_H
+
+/* Compare with sigcode() in riscv/riscv/locore.S */
+static inline abi_long setup_sigtramp(abi_ulong offset, unsigned sigf_uc,
+ unsigned sys_sigreturn)
+{
+ int i;
+ uint32_t sys_exit = TARGET_FREEBSD_NR_exit;
+
+ static const uint32_t sigtramp_code[] = {
+ /* 1 */ const_le32(0x00010513), /* mv a0, sp */
+ /* 2 */ const_le32(0x00050513 + (sigf_uc << 20)), /* addi a0, a0,
sigf_uc */
+ /* 3 */ const_le32(0x00000293 + (sys_sigreturn << 20)), /* li t0,
sys_sigreturn */
+ /* 4 */ const_le32(0x00000073), /* ecall */
+ /* 5 */ const_le32(0x00000293 + (sys_exit << 20)), /* li t0, sys_exit
*/
+ /* 6 */ const_le32(0x00000073), /* ecall */
+ /* 7 */ const_le32(0xFF1FF06F) /* b -16 */
+ };
+
+ return memcpy_to_target(offset, sigtramp_code, TARGET_SZSIGCODE);
+}
+#endif /* TARGET_ARCH_SIGTRAMP_H */
--
2.34.1
- [PATCH v3 00/17] bsd-user: Comprehensive RISCV Support, Ajeet Singh, 2024/08/24
- [PATCH v3 01/17] bsd-user: Implement RISC-V CPU initialization and main loop, Ajeet Singh, 2024/08/24
- [PATCH v3 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling, Ajeet Singh, 2024/08/24
- [PATCH v3 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions, Ajeet Singh, 2024/08/24
- [PATCH v3 04/17] bsd-user: Implement RISC-V TLS register setup, Ajeet Singh, 2024/08/24
- [PATCH v3 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection, Ajeet Singh, 2024/08/24
- [PATCH v3 06/17] bsd-user: Define RISC-V register structures and register copying, Ajeet Singh, 2024/08/24
- [PATCH v3 08/17] bsd-user: Implement RISC-V sysarch system call emulation, Ajeet Singh, 2024/08/24
- [PATCH v3 07/17] bsd-user: Add RISC-V signal trampoline setup function,
Ajeet Singh <=
- [PATCH v3 09/17] bsd-user: Add RISC-V thread setup and initialization support, Ajeet Singh, 2024/08/24
- [PATCH v3 10/17] bsd-user: Define RISC-V VM parameters and helper functions, Ajeet Singh, 2024/08/24
- [PATCH v3 11/17] bsd-user: Define RISC-V system call structures and constants, Ajeet Singh, 2024/08/24
- [PATCH v3 12/17] bsd-user: Add generic RISC-V64 target definitions, Ajeet Singh, 2024/08/24
- [PATCH v3 13/17] bsd-user: Define RISC-V signal handling structures and constants, Ajeet Singh, 2024/08/24
- [PATCH v3 14/17] bsd-user: Implement RISC-V signal trampoline setup functions, Ajeet Singh, 2024/08/24
- [PATCH v3 15/17] bsd-user: Implement 'get_mcontext' for RISC-V, Ajeet Singh, 2024/08/24
- [PATCH v3 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV, Ajeet Singh, 2024/08/24
- [PATCH v3 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files, Ajeet Singh, 2024/08/24