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[PATCH v10 01/21] target/riscv: expose *envcfg csr and priv to qemu-user
From: |
Deepak Gupta |
Subject: |
[PATCH v10 01/21] target/riscv: expose *envcfg csr and priv to qemu-user as well |
Date: |
Tue, 27 Aug 2024 16:18:45 -0700 |
Execution environment config CSR controlling user env and current
privilege state shouldn't be limited to qemu-system only. *envcfg
CSRs control enabling of features in next lesser mode. In some cases
bits *envcfg CSR can be lit up by kernel as part of kernel policy or
software (user app) can choose to opt-in by issuing a system call
(e.g. prctl). In case of qemu-user, it should be no different because
qemu is providing underlying execution environment facility and thus
either should provide some default value in *envcfg CSRs or react to
system calls (prctls) initiated from application.
`henvcfg` has been left for qemu-system only because it is not expected
that someone will use qemu-user where application is expected to have
hypervisor underneath which is controlling its execution environment. If
such a need arises then `henvcfg` could be exposed as well.
Relevant discussion:
CAKmqyKOTVWPFep2msTQVdUmJErkH+bqCcKEQ4hAnyDFPdWKe0Q@mail.gmail.com/">https://lore.kernel.org/all/CAKmqyKOTVWPFep2msTQVdUmJErkH+bqCcKEQ4hAnyDFPdWKe0Q@mail.gmail.com/
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.h | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 87742047ce..270a2a031c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -226,8 +226,12 @@ struct CPUArchState {
uint32_t elf_flags;
#endif
-#ifndef CONFIG_USER_ONLY
target_ulong priv;
+ /* CSRs for execution environment configuration */
+ uint64_t menvcfg;
+ target_ulong senvcfg;
+
+#ifndef CONFIG_USER_ONLY
/* This contains QEMU specific information about the virt state. */
bool virt_enabled;
target_ulong geilen;
@@ -429,12 +433,9 @@ struct CPUArchState {
target_ulong upmmask;
target_ulong upmbase;
- /* CSRs for execution environment configuration */
- uint64_t menvcfg;
uint64_t mstateen[SMSTATEEN_MAX_COUNT];
uint64_t hstateen[SMSTATEEN_MAX_COUNT];
uint64_t sstateen[SMSTATEEN_MAX_COUNT];
- target_ulong senvcfg;
uint64_t henvcfg;
#endif
target_ulong cur_pmmask;
--
2.44.0
- [PATCH v10 00/21] riscv support for control flow integrity extensions, Deepak Gupta, 2024/08/27
- [PATCH v10 03/21] target/riscv: Add zicfilp extension, Deepak Gupta, 2024/08/27
- [PATCH v10 05/21] target/riscv: save and restore elp state on priv transitions, Deepak Gupta, 2024/08/27
- [PATCH v10 02/21] linux-user/riscv: set priv for qemu-user and defaults for *envcfg, Deepak Gupta, 2024/08/27
- [PATCH v10 06/21] target/riscv: additional code information for sw check, Deepak Gupta, 2024/08/27
- [PATCH v10 01/21] target/riscv: expose *envcfg csr and priv to qemu-user as well,
Deepak Gupta <=
- [PATCH v10 08/21] target/riscv: zicfilp `lpad` impl and branch tracking, Deepak Gupta, 2024/08/27
- [PATCH v10 04/21] target/riscv: Introduce elp state and enabling controls for zicfilp, Deepak Gupta, 2024/08/27
- [PATCH v10 11/21] target/riscv: Add zicfiss extension, Deepak Gupta, 2024/08/27
- [PATCH v10 09/21] disas/riscv: enable `lpad` disassembly, Deepak Gupta, 2024/08/27
- [PATCH v10 10/21] target/riscv: Expose zicfilp extension as a cpu property, Deepak Gupta, 2024/08/27
- [PATCH v10 07/21] target/riscv: tracking indirect branches (fcfi) for zicfilp, Deepak Gupta, 2024/08/27
- [PATCH v10 13/21] target/riscv: tb flag for shadow stack instructions, Deepak Gupta, 2024/08/27