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[PATCH v10 18/21] target/riscv: compressed encodings for sspush and sspo
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From: |
Deepak Gupta |
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Subject: |
[PATCH v10 18/21] target/riscv: compressed encodings for sspush and sspopchk |
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Date: |
Tue, 27 Aug 2024 16:19:02 -0700 |
sspush/sspopchk have compressed encodings carved out of zcmops.
compressed sspush is designated as c.mop.1 while compressed sspopchk
is designated as c.mop.5.
Note that c.sspush x1 exists while c.sspush x5 doesn't. Similarly
c.sspopchk x5 exists while c.sspopchk x1 doesn't.
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Co-developed-by: Jim Shu <jim.shu@sifive.com>
Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn16.decode | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 3953bcf82d..bf893d1c2e 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -140,6 +140,10 @@ sw 110 ... ... .. ... 00 @cs_w
addi 000 . ..... ..... 01 @ci
addi 010 . ..... ..... 01 @c_li
{
+ # c.sspush x1 carving out of zcmops
+ sspush 011 0 00001 00000 01 &r2_s rs2=1 rs1=0
+ # c.sspopchk x5 carving out of zcmops
+ sspopchk 011 0 00101 00000 01 &r2 rs1=5 rd=0
c_mop_n 011 0 0 n:3 1 00000 01
illegal 011 0 ----- 00000 01 # c.addi16sp and c.lui, RES nzimm=0
addi 011 . 00010 ..... 01 @c_addi16sp
--
2.44.0
- [PATCH v10 10/21] target/riscv: Expose zicfilp extension as a cpu property, (continued)
- [PATCH v10 10/21] target/riscv: Expose zicfilp extension as a cpu property, Deepak Gupta, 2024/08/27
- [PATCH v10 07/21] target/riscv: tracking indirect branches (fcfi) for zicfilp, Deepak Gupta, 2024/08/27
- [PATCH v10 13/21] target/riscv: tb flag for shadow stack instructions, Deepak Gupta, 2024/08/27
- [PATCH v10 17/21] target/riscv: implement zicfiss instructions, Deepak Gupta, 2024/08/27
- [PATCH v10 12/21] target/riscv: introduce ssp and enabling controls for zicfiss, Deepak Gupta, 2024/08/27
- [PATCH v10 20/21] disas/riscv: enable disassembly for compressed sspush/sspopchk, Deepak Gupta, 2024/08/27
- [PATCH v10 14/21] target/riscv: mmu changes for zicfiss shadow stack protection, Deepak Gupta, 2024/08/27
- [PATCH v10 15/21] target/riscv: AMO operations always raise store/AMO fault, Deepak Gupta, 2024/08/27
- [PATCH v10 16/21] target/riscv: update `decode_save_opc` to store extra word2, Deepak Gupta, 2024/08/27
- [PATCH v10 18/21] target/riscv: compressed encodings for sspush and sspopchk,
Deepak Gupta <=
- [PATCH v10 21/21] target/riscv: Expose zicfiss extension as a cpu property, Deepak Gupta, 2024/08/27
- [PATCH v10 19/21] disas/riscv: enable disassembly for zicfiss instructions, Deepak Gupta, 2024/08/27
- Re: [PATCH v10 00/21] riscv support for control flow integrity extensions, Deepak Gupta, 2024/08/27
- Re: [PATCH v10 00/21] riscv support for control flow integrity extensions, Alistair Francis, 2024/08/27