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Re: [PATCH v11 15/20] target/riscv: update `decode_save_opc` to store ex
|
From: |
Alistair Francis |
|
Subject: |
Re: [PATCH v11 15/20] target/riscv: update `decode_save_opc` to store extra word2 |
|
Date: |
Thu, 29 Aug 2024 09:36:07 +1000 |
On Thu, Aug 29, 2024 at 3:51 AM Deepak Gupta <debug@rivosinc.com> wrote:
>
> Extra word 2 is stored during tcg compile and `decode_save_opc` needs
> additional argument in order to pass the value. This will be used during
> unwind to get extra information about instruction like how to massage
> exceptions. Updated all callsites as well.
Woo!
This should fix https://gitlab.com/qemu-project/qemu/-/issues/594 as well
>
> Signed-off-by: Deepak Gupta <debug@rivosinc.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/594
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_privileged.c.inc | 8 ++++----
> target/riscv/insn_trans/trans_rva.c.inc | 4 ++--
> target/riscv/insn_trans/trans_rvd.c.inc | 4 ++--
> target/riscv/insn_trans/trans_rvf.c.inc | 4 ++--
> target/riscv/insn_trans/trans_rvh.c.inc | 8 ++++----
> target/riscv/insn_trans/trans_rvi.c.inc | 6 +++---
> target/riscv/insn_trans/trans_rvvk.c.inc | 10 +++++-----
> target/riscv/insn_trans/trans_rvzacas.c.inc | 4 ++--
> target/riscv/insn_trans/trans_rvzfh.c.inc | 4 ++--
> target/riscv/insn_trans/trans_svinval.c.inc | 6 +++---
> target/riscv/translate.c | 11 ++++++-----
> 11 files changed, 35 insertions(+), 34 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_privileged.c.inc
> b/target/riscv/insn_trans/trans_privileged.c.inc
> index bc5263a4e0..ecd3b8b2c9 100644
> --- a/target/riscv/insn_trans/trans_privileged.c.inc
> +++ b/target/riscv/insn_trans/trans_privileged.c.inc
> @@ -78,7 +78,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
> {
> #ifndef CONFIG_USER_ONLY
> if (has_ext(ctx, RVS)) {
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> translator_io_start(&ctx->base);
> gen_helper_sret(cpu_pc, tcg_env);
> exit_tb(ctx); /* no chaining */
> @@ -95,7 +95,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
> static bool trans_mret(DisasContext *ctx, arg_mret *a)
> {
> #ifndef CONFIG_USER_ONLY
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> translator_io_start(&ctx->base);
> gen_helper_mret(cpu_pc, tcg_env);
> exit_tb(ctx); /* no chaining */
> @@ -109,7 +109,7 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
> static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
> {
> #ifndef CONFIG_USER_ONLY
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> gen_update_pc(ctx, ctx->cur_insn_len);
> gen_helper_wfi(tcg_env);
> return true;
> @@ -121,7 +121,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
> static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
> {
> #ifndef CONFIG_USER_ONLY
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> gen_helper_tlb_flush(tcg_env);
> return true;
> #endif
> diff --git a/target/riscv/insn_trans/trans_rva.c.inc
> b/target/riscv/insn_trans/trans_rva.c.inc
> index 39bbf60f3c..9cf3ae8019 100644
> --- a/target/riscv/insn_trans/trans_rva.c.inc
> +++ b/target/riscv/insn_trans/trans_rva.c.inc
> @@ -34,7 +34,7 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp
> mop)
> {
> TCGv src1;
>
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> src1 = get_address(ctx, a->rs1, 0);
> if (a->rl) {
> tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
> @@ -61,7 +61,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp
> mop)
> TCGLabel *l1 = gen_new_label();
> TCGLabel *l2 = gen_new_label();
>
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> src1 = get_address(ctx, a->rs1, 0);
> tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
>
> diff --git a/target/riscv/insn_trans/trans_rvd.c.inc
> b/target/riscv/insn_trans/trans_rvd.c.inc
> index 1f5fac65a2..d779ec75c7 100644
> --- a/target/riscv/insn_trans/trans_rvd.c.inc
> +++ b/target/riscv/insn_trans/trans_rvd.c.inc
> @@ -51,7 +51,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
> memop |= MO_ATOM_WITHIN16;
> }
>
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> addr = get_address(ctx, a->rs1, a->imm);
> tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, memop);
>
> @@ -71,7 +71,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
> memop |= MO_ATOM_WITHIN16;
> }
>
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> addr = get_address(ctx, a->rs1, a->imm);
> tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, memop);
> return true;
> diff --git a/target/riscv/insn_trans/trans_rvf.c.inc
> b/target/riscv/insn_trans/trans_rvf.c.inc
> index f771aa1939..084c184e65 100644
> --- a/target/riscv/insn_trans/trans_rvf.c.inc
> +++ b/target/riscv/insn_trans/trans_rvf.c.inc
> @@ -52,7 +52,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
> memop |= MO_ATOM_WITHIN16;
> }
>
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> addr = get_address(ctx, a->rs1, a->imm);
> dest = cpu_fpr[a->rd];
> tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, memop);
> @@ -74,7 +74,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
> memop |= MO_ATOM_WITHIN16;
> }
>
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> addr = get_address(ctx, a->rs1, a->imm);
> tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, memop);
> return true;
> diff --git a/target/riscv/insn_trans/trans_rvh.c.inc
> b/target/riscv/insn_trans/trans_rvh.c.inc
> index aa9d41c18c..03c6694430 100644
> --- a/target/riscv/insn_trans/trans_rvh.c.inc
> +++ b/target/riscv/insn_trans/trans_rvh.c.inc
> @@ -44,7 +44,7 @@ static bool do_hlv(DisasContext *ctx, arg_r2 *a,
> TCGv dest = dest_gpr(ctx, a->rd);
> TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
>
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> func(dest, tcg_env, addr);
> gen_set_gpr(ctx, a->rd, dest);
> return true;
> @@ -56,7 +56,7 @@ static bool do_hsv(DisasContext *ctx, arg_r2_s *a,
> TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
> TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
>
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> func(tcg_env, addr, data);
> return true;
> }
> @@ -147,7 +147,7 @@ static bool trans_hfence_gvma(DisasContext *ctx,
> arg_sfence_vma *a)
> {
> REQUIRE_EXT(ctx, RVH);
> #ifndef CONFIG_USER_ONLY
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> gen_helper_hyp_gvma_tlb_flush(tcg_env);
> return true;
> #endif
> @@ -158,7 +158,7 @@ static bool trans_hfence_vvma(DisasContext *ctx,
> arg_sfence_vma *a)
> {
> REQUIRE_EXT(ctx, RVH);
> #ifndef CONFIG_USER_ONLY
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> gen_helper_hyp_tlb_flush(tcg_env);
> return true;
> #endif
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
> b/target/riscv/insn_trans/trans_rvi.c.inc
> index b427f3a939..a619ea7c0e 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -326,7 +326,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp
> memop)
> if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) {
> memop |= MO_ATOM_WITHIN16;
> }
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> if (get_xl(ctx) == MXL_RV128) {
> out = gen_load_i128(ctx, a, memop);
> } else {
> @@ -427,7 +427,7 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp
> memop)
> if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) {
> memop |= MO_ATOM_WITHIN16;
> }
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> if (get_xl(ctx) == MXL_RV128) {
> return gen_store_i128(ctx, a, memop);
> } else {
> @@ -889,7 +889,7 @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i
> *a)
> static bool do_csr_post(DisasContext *ctx)
> {
> /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> /* We may have changed important cpu state -- exit to main loop. */
> gen_update_pc(ctx, ctx->cur_insn_len);
> exit_tb(ctx);
> diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc
> b/target/riscv/insn_trans/trans_rvvk.c.inc
> index ae1f40174a..27bf3f0b68 100644
> --- a/target/riscv/insn_trans/trans_rvvk.c.inc
> +++ b/target/riscv/insn_trans/trans_rvvk.c.inc
> @@ -249,7 +249,7 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx,
> vwsll_vx_check)
>
> \
> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
> \
> /* save opcode for unwinding in case we throw an exception
> */ \
> - decode_save_opc(s);
> \
> + decode_save_opc(s, 0);
> \
> egs = tcg_constant_i32(EGS);
> \
> gen_helper_egs_check(egs, tcg_env);
> \
> }
> \
> @@ -322,7 +322,7 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
>
> \
> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
> \
> /* save opcode for unwinding in case we throw an exception
> */ \
> - decode_save_opc(s);
> \
> + decode_save_opc(s, 0);
> \
> egs = tcg_constant_i32(EGS);
> \
> gen_helper_egs_check(egs, tcg_env);
> \
> }
> \
> @@ -389,7 +389,7 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check,
> ZVKNED_EGS)
>
> \
> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
> \
> /* save opcode for unwinding in case we throw an exception
> */ \
> - decode_save_opc(s);
> \
> + decode_save_opc(s, 0);
> \
> egs = tcg_constant_i32(EGS);
> \
> gen_helper_egs_check(egs, tcg_env);
> \
> }
> \
> @@ -440,7 +440,7 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
>
> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
> /* save opcode for unwinding in case we throw an exception */
> - decode_save_opc(s);
> + decode_save_opc(s, 0);
> egs = tcg_constant_i32(ZVKNH_EGS);
> gen_helper_egs_check(egs, tcg_env);
> }
> @@ -471,7 +471,7 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
>
> if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
> /* save opcode for unwinding in case we throw an exception */
> - decode_save_opc(s);
> + decode_save_opc(s, 0);
> egs = tcg_constant_i32(ZVKNH_EGS);
> gen_helper_egs_check(egs, tcg_env);
> }
> diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc
> b/target/riscv/insn_trans/trans_rvzacas.c.inc
> index fcced99fc7..15e688a033 100644
> --- a/target/riscv/insn_trans/trans_rvzacas.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzacas.c.inc
> @@ -76,7 +76,7 @@ static bool gen_cmpxchg64(DisasContext *ctx, arg_atomic *a,
> MemOp mop)
> TCGv src1 = get_address(ctx, a->rs1, 0);
> TCGv_i64 src2 = get_gpr_pair(ctx, a->rs2);
>
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
> tcg_gen_atomic_cmpxchg_i64(dest, src1, dest, src2, ctx->mem_idx, mop);
>
> gen_set_gpr_pair(ctx, a->rd, dest);
> @@ -121,7 +121,7 @@ static bool trans_amocas_q(DisasContext *ctx,
> arg_amocas_q *a)
>
> tcg_gen_concat_i64_i128(src2, src2l, src2h);
> tcg_gen_concat_i64_i128(dest, destl, desth);
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
> tcg_gen_atomic_cmpxchg_i128(dest, src1, dest, src2, ctx->mem_idx,
> (MO_ALIGN | MO_TEUO));
>
> diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc
> b/target/riscv/insn_trans/trans_rvzfh.c.inc
> index 1eb458b491..bece48e600 100644
> --- a/target/riscv/insn_trans/trans_rvzfh.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
> @@ -48,7 +48,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a)
> REQUIRE_FPU;
> REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);
>
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> t0 = get_gpr(ctx, a->rs1, EXT_NONE);
> if (a->imm) {
> TCGv temp = tcg_temp_new();
> @@ -71,7 +71,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
> REQUIRE_FPU;
> REQUIRE_ZFHMIN_OR_ZFBFMIN(ctx);
>
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> t0 = get_gpr(ctx, a->rs1, EXT_NONE);
> if (a->imm) {
> TCGv temp = tcg_temp_new();
> diff --git a/target/riscv/insn_trans/trans_svinval.c.inc
> b/target/riscv/insn_trans/trans_svinval.c.inc
> index 0f692a1088..a06c3b214f 100644
> --- a/target/riscv/insn_trans/trans_svinval.c.inc
> +++ b/target/riscv/insn_trans/trans_svinval.c.inc
> @@ -28,7 +28,7 @@ static bool trans_sinval_vma(DisasContext *ctx,
> arg_sinval_vma *a)
> /* Do the same as sfence.vma currently */
> REQUIRE_EXT(ctx, RVS);
> #ifndef CONFIG_USER_ONLY
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> gen_helper_tlb_flush(tcg_env);
> return true;
> #endif
> @@ -57,7 +57,7 @@ static bool trans_hinval_vvma(DisasContext *ctx,
> arg_hinval_vvma *a)
> /* Do the same as hfence.vvma currently */
> REQUIRE_EXT(ctx, RVH);
> #ifndef CONFIG_USER_ONLY
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> gen_helper_hyp_tlb_flush(tcg_env);
> return true;
> #endif
> @@ -70,7 +70,7 @@ static bool trans_hinval_gvma(DisasContext *ctx,
> arg_hinval_gvma *a)
> /* Do the same as hfence.gvma currently */
> REQUIRE_EXT(ctx, RVH);
> #ifndef CONFIG_USER_ONLY
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> gen_helper_hyp_gvma_tlb_flush(tcg_env);
> return true;
> #endif
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 16fff70dac..e677062a10 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -209,11 +209,12 @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64
> in)
> tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
> }
>
> -static void decode_save_opc(DisasContext *ctx)
> +static void decode_save_opc(DisasContext *ctx, target_ulong excp_uw2)
> {
> assert(!ctx->insn_start_updated);
> ctx->insn_start_updated = true;
> tcg_set_insn_start_param(ctx->base.insn_start, 1, ctx->opcode);
> + tcg_set_insn_start_param(ctx->base.insn_start, 2, excp_uw2);
> }
>
> static void gen_pc_plus_diff(TCGv target, DisasContext *ctx,
> @@ -699,7 +700,7 @@ static void gen_set_rm(DisasContext *ctx, int rm)
> }
>
> /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> gen_helper_set_rounding_mode(tcg_env, tcg_constant_i32(rm));
> }
>
> @@ -712,7 +713,7 @@ static void gen_set_rm_chkfrm(DisasContext *ctx, int rm)
> ctx->frm_valid = true;
>
> /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, 0);
> gen_helper_set_rounding_mode_chkfrm(tcg_env, tcg_constant_i32(rm));
> }
>
> @@ -1096,7 +1097,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
> mop |= MO_ALIGN;
> }
>
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
> src1 = get_address(ctx, a->rs1, 0);
> func(dest, src1, src2, ctx->mem_idx, mop);
>
> @@ -1110,7 +1111,7 @@ static bool gen_cmpxchg(DisasContext *ctx, arg_atomic
> *a, MemOp mop)
> TCGv src1 = get_address(ctx, a->rs1, 0);
> TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
>
> - decode_save_opc(ctx);
> + decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
> tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop);
>
> gen_set_gpr(ctx, a->rd, dest);
> --
> 2.44.0
>
>
- Re: [PATCH v11 13/20] target/riscv: mmu changes for zicfiss shadow stack protection, (continued)
[PATCH v11 18/20] disas/riscv: enable disassembly for zicfiss instructions, Deepak Gupta, 2024/08/28
[PATCH v11 20/20] target/riscv: Expose zicfiss extension as a cpu property, Deepak Gupta, 2024/08/28
[PATCH v11 19/20] disas/riscv: enable disassembly for compressed sspush/sspopchk, Deepak Gupta, 2024/08/28
[PATCH v11 15/20] target/riscv: update `decode_save_opc` to store extra word2, Deepak Gupta, 2024/08/28
- Re: [PATCH v11 15/20] target/riscv: update `decode_save_opc` to store extra word2,
Alistair Francis <=
Re: [PATCH v11 00/20] riscv support for control flow integrity extensions, Deepak Gupta, 2024/08/28