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Re: [PATCH v2 7/7] hw/net/can/xlnx-versal-canfd: Fix FIFO issues
From: |
Doug Brown |
Subject: |
Re: [PATCH v2 7/7] hw/net/can/xlnx-versal-canfd: Fix FIFO issues |
Date: |
Thu, 29 Aug 2024 17:11:35 -0700 |
User-agent: |
Mozilla Thunderbird |
Hi Pavel,
On 8/29/2024 6:24 AM, Pavel Pisa wrote:
> Generally, I agree that index should wrap up for cyclic FIFO
> implementation and change looks logical to me but I do not
> see and studied all consequences related to emulated HW.
>
> If that is confirmed or corrected by somebody from AMD/XilinX,
> it would be better. I can find more time to do deeper analysis
> if no other looks into the whole code.
Thank you for your reviews! I agree. I don't know how the hardware is
actually implemented internally so it would be great if someone from AMD
could confirm that this change 100% matches the hardware. Unfortunately
Versal dev boards are very expensive so I can't test hardware myself.
What I can say is that before I implemented the index calculation fixes
in this patch, the Linux driver in the Xilinx kernel was seeing
incorrect messages. Now it works fine even with heavy bus load.
Doug
- [PATCH v2 1/7] hw/net/can/xlnx-versal-canfd: Fix interrupt level, (continued)
- [PATCH v2 1/7] hw/net/can/xlnx-versal-canfd: Fix interrupt level, Doug Brown, 2024/08/26
- [PATCH v2 2/7] hw/net/can/xlnx-versal-canfd: Fix CAN FD flag check, Doug Brown, 2024/08/26
- [PATCH v2 3/7] hw/net/can/xlnx-versal-canfd: Translate CAN ID registers, Doug Brown, 2024/08/26
- [PATCH v2 4/7] hw/net/can/xlnx-versal-canfd: Handle flags correctly, Doug Brown, 2024/08/26
- [PATCH v2 7/7] hw/net/can/xlnx-versal-canfd: Fix FIFO issues, Doug Brown, 2024/08/26
- [PATCH v2 5/7] hw/net/can/xlnx-versal-canfd: Fix byte ordering, Doug Brown, 2024/08/26
- [PATCH v2 6/7] hw/net/can/xlnx-versal-canfd: Simplify DLC conversions, Doug Brown, 2024/08/26