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[PATCH v2 09/14] tcg/riscv: Implement vector neg ops
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From: |
LIU Zhiwei |
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Subject: |
[PATCH v2 09/14] tcg/riscv: Implement vector neg ops |
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Date: |
Fri, 30 Aug 2024 14:16:02 +0800 |
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
---
tcg/riscv/tcg-target.c.inc | 8 ++++++++
tcg/riscv/tcg-target.h | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 1e8c0fb031..4fc82481a7 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -322,6 +322,7 @@ typedef enum {
OPC_VXOR_VV = 0x2c000057 | V_OPIVV,
OPC_VXOR_VI = 0x2c000057 | V_OPIVI,
+ OPC_VRSUB_VI = 0xc000057 | V_OPIVI,
OPC_VMSEQ_VV = 0x60000057 | V_OPIVV,
OPC_VMSEQ_VI = 0x60000057 | V_OPIVI,
OPC_VMSEQ_VX = 0x60000057 | V_OPIVX,
@@ -2394,6 +2395,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
riscv_set_vec_config_vl(s, type);
tcg_out_opc_vi(s, OPC_VXOR_VI, a0, a1, -1, true);
break;
+ case INDEX_op_neg_vec:
+ riscv_set_vec_config_vl_vece(s, type, vece);
+ tcg_out_opc_vi(s, OPC_VRSUB_VI, a0, a1, 0, true);
+ break;
case INDEX_op_rvv_cmp_vx:
riscv_set_vec_config_vl_vece(s, type, vece);
tcg_out_cmp_vec_vx(s, a2, a0, a1);
@@ -2408,6 +2413,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_cmp_vec_vv(s, a2, a0, a1);
break;
case INDEX_op_rvv_merge_vec:
+ riscv_set_vec_config_vl_vece(s, type, vece);
if (const_args[2]) {
/* vd[i] == v0.mask[i] ? imm : vs2[i] */
tcg_out_opc_vim_mask(s, OPC_VMERGE_VIM, a0, a1, a2);
@@ -2520,6 +2526,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_or_vec:
case INDEX_op_xor_vec:
case INDEX_op_not_vec:
+ case INDEX_op_neg_vec:
return 1;
case INDEX_op_cmp_vec:
return -1;
@@ -2673,6 +2680,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_dupm_vec:
case INDEX_op_ld_vec:
return C_O1_I1(v, r);
+ case INDEX_op_neg_vec:
case INDEX_op_not_vec:
return C_O1_I1(v, v);
case INDEX_op_add_vec:
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index acb8dfdf16..401696d639 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -152,7 +152,7 @@ typedef enum {
#define TCG_TARGET_HAS_nor_vec 0
#define TCG_TARGET_HAS_eqv_vec 0
#define TCG_TARGET_HAS_not_vec 1
-#define TCG_TARGET_HAS_neg_vec 0
+#define TCG_TARGET_HAS_neg_vec 1
#define TCG_TARGET_HAS_abs_vec 0
#define TCG_TARGET_HAS_roti_vec 0
#define TCG_TARGET_HAS_rots_vec 0
--
2.43.0
- [PATCH v2 00/14] tcg/riscv: Add support for vector, LIU Zhiwei, 2024/08/30
- [PATCH v2 01/14] tcg/op-gvec: Fix iteration step in 32-bit operation, LIU Zhiwei, 2024/08/30
- [PATCH v2 02/14] util: Add RISC-V vector extension probe in cpuinfo, LIU Zhiwei, 2024/08/30
- [PATCH v2 03/14] tcg/riscv: Add basic support for vector, LIU Zhiwei, 2024/08/30
- [PATCH v2 04/14] tcg/riscv: Add riscv vset{i}vli support, LIU Zhiwei, 2024/08/30
- [PATCH v2 05/14] tcg/riscv: Implement vector load/store, LIU Zhiwei, 2024/08/30
- [PATCH v2 06/14] tcg/riscv: Implement vector mov/dup{m/i}, LIU Zhiwei, 2024/08/30
- [PATCH v2 07/14] tcg/riscv: Add support for basic vector opcodes, LIU Zhiwei, 2024/08/30
- [PATCH v2 08/14] tcg/riscv: Implement vector cmp ops, LIU Zhiwei, 2024/08/30
- [PATCH v2 09/14] tcg/riscv: Implement vector neg ops,
LIU Zhiwei <=
- [PATCH v2 10/14] tcg/riscv: Implement vector sat/mul ops, LIU Zhiwei, 2024/08/30
- [PATCH v2 11/14] tcg/riscv: Implement vector min/max ops, LIU Zhiwei, 2024/08/30
- [PATCH v2 12/14] tcg/riscv: Implement vector shs/v ops, LIU Zhiwei, 2024/08/30
- [PATCH v2 13/14] tcg/riscv: Implement vector roti/v/x shi ops, LIU Zhiwei, 2024/08/30
- [PATCH v2 14/14] tcg/riscv: Enable native vector support for TCG host, LIU Zhiwei, 2024/08/30