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[PATCH v3 08/11] aspeed/soc: Introduce a new API to get the device irq
From: |
Jamin Lin |
Subject: |
[PATCH v3 08/11] aspeed/soc: Introduce a new API to get the device irq |
Date: |
Tue, 3 Sep 2024 16:35:25 +0800 |
Currently, users can set the INTC mapping table with
enumerated device id and device irq to get the INTC orgate
input pins. However, some devices use the continuous source numbers in the
same INTC orgate. To reduce the enumerated device id definition,
create a new API to get the INTC orgate input pin
if users only provide the device id with its bus number index.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 4257b5e8af..a5eb78524f 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -193,6 +193,27 @@ static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState
*s, int dev)
return qdev_get_gpio_in(DEVICE(&a->gic), sc->irqmap[dev]);
}
+static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev,
+ int index)
+{
+ Aspeed27x0SoCState *a = ASPEED27X0_SOC(s);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(aspeed_soc_ast2700_gic_intcmap); i++) {
+ if (sc->irqmap[dev] == aspeed_soc_ast2700_gic_intcmap[i].irq) {
+ assert(aspeed_soc_ast2700_gic_intcmap[i].ptr);
+ return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]),
+ aspeed_soc_ast2700_gic_intcmap[i].ptr[dev] + index);
+ }
+ }
+
+ /*
+ * Invalid orgate index, device irq should be 128 to 136.
+ */
+ g_assert_not_reached();
+}
+
static uint64_t aspeed_ram_capacity_read(void *opaque, hwaddr addr,
unsigned int size)
{
--
2.34.1
- [PATCH v3 00/11] support I2C for AST2700, Jamin Lin, 2024/09/03
- [PATCH v3 01/11] hw/i2c/aspeed: Support discontinuous register memory region of I2C bus, Jamin Lin, 2024/09/03
- [PATCH v3 02/11] hw/i2c/aspeed: Introduce a new bus pool buffer attribute in AspeedI2Cbus, Jamin Lin, 2024/09/03
- [PATCH v3 03/11] hw/i2c/aspeed: Support discontinuous poll buffer memory region of I2C bus, Jamin Lin, 2024/09/03
- [PATCH v3 04/11] hw/i2c/aspeed: Introduce a new dma_dram_offset attribute in AspeedI2Cbus, Jamin Lin, 2024/09/03
- [PATCH v3 06/11] hw/i2c/aspeed: Add support for Tx/Rx buffer 64 bit addresses, Jamin Lin, 2024/09/03
- [PATCH v3 05/11] hw/i2c/aspeed: Add AST2700 support, Jamin Lin, 2024/09/03
- [PATCH v3 07/11] hw/i2c/aspeed: Add support for 64 bit addresses, Jamin Lin, 2024/09/03
- [PATCH v3 09/11] aspeed/soc: Support I2C for AST2700, Jamin Lin, 2024/09/03
- [PATCH v3 08/11] aspeed/soc: Introduce a new API to get the device irq,
Jamin Lin <=
- [PATCH v3 10/11] aspeed: Add tmp105 in i2c bus 0 for AST2700, Jamin Lin, 2024/09/03
- [PATCH v3 11/11] machine_aspeed.py: Update to test I2C for AST2700, Jamin Lin, 2024/09/03
- Re: [SPAM] [PATCH v3 00/11] support I2C for AST2700, Cédric Le Goater, 2024/09/03