Re: Are floating-point exceptions usable on AArch64?

[Peter Maydell]

On Wed, 4 Sept 2024 at 11:32, Sebastian Huber
<sebastian.huber@embedded-brains.de> wrote:
> I tried to provoke a division-by-zero exception on AArch64 using:
>
>     uint64_t value;
>     __asm__ volatile (
>       "mrs %0, FPCR\n"
>       "orr %0, %0, 0x200\n"
>       "msr FPCR, %0" :  "=&r" ( value ) : : "memory"
>     );
>     volatile double x = 0x0;
>     volatile double y = 0x0;
>     x /= y;
>
> When I look with the debugger at $fpcr it still says 0x0
> after the msr. Are floating-point exceptions usable on
> AArch64 in general?

Floating point exceptions, in the sense of "when the
exception condition happens the cumulative exception bit
in the FPSR is set", work. What you're trying to use here is what
the architecture calls "trapped exception handling", where
you set the DZE etc bits in the FPCR to get a CPU exception
instead of it updating the FPSR bit. Those are architecturally
optional, and QEMU's CPU implementation doesn't implement them.
(Nor do most real hardware implementations AFAIK.)

thanks
-- PMM