[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v6 08/17] bsd-user: Implement RISC-V sysarch system call emulatio
From: |
Ajeet Singh |
Subject: |
[PATCH v6 08/17] bsd-user: Implement RISC-V sysarch system call emulation |
Date: |
Mon, 16 Sep 2024 01:25:45 +1000 |
From: Mark Corbin <mark@dibsco.co.uk>
Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch'
system call for the RISC-V architecture.
Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that
the operation is not supported.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
bsd-user/riscv/target_arch_sysarch.h | 41 ++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 bsd-user/riscv/target_arch_sysarch.h
diff --git a/bsd-user/riscv/target_arch_sysarch.h
b/bsd-user/riscv/target_arch_sysarch.h
new file mode 100644
index 0000000000..9af42331b4
--- /dev/null
+++ b/bsd-user/riscv/target_arch_sysarch.h
@@ -0,0 +1,41 @@
+/*
+ * RISC-V sysarch() system call emulation
+ *
+ * Copyright (c) 2019 Mark Corbin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_SYSARCH_H
+#define TARGET_ARCH_SYSARCH_H
+
+#include "target_syscall.h"
+#include "target_arch.h"
+
+static inline abi_long do_freebsd_arch_sysarch(CPURISCVState *env, int op,
+ abi_ulong parms)
+{
+
+ return -TARGET_EOPNOTSUPP;
+}
+
+static inline void do_freebsd_arch_print_sysarch(
+ const struct syscallname *name, abi_long arg1, abi_long arg2,
+ abi_long arg3, abi_long arg4, abi_long arg5, abi_long arg6)
+{
+
+ gemu_log("UNKNOWN OP: %d, " TARGET_ABI_FMT_lx ")", (int)arg1, arg2);
+}
+
+#endif /* TARGET_ARCH_SYSARCH_H */
--
2.34.1
- [PATCH v6 00/17] bsd-user: Comprehensive RISCV Support, Ajeet Singh, 2024/09/15
- [PATCH v6 01/17] bsd-user: Implement RISC-V CPU initialization and main loop, Ajeet Singh, 2024/09/15
- [PATCH v6 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling, Ajeet Singh, 2024/09/15
- [PATCH v6 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions, Ajeet Singh, 2024/09/15
- [PATCH v6 04/17] bsd-user: Implement RISC-V TLS register setup, Ajeet Singh, 2024/09/15
- [PATCH v6 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection, Ajeet Singh, 2024/09/15
- [PATCH v6 06/17] bsd-user: Define RISC-V register structures and register copying, Ajeet Singh, 2024/09/15
- [PATCH v6 07/17] bsd-user: Add RISC-V signal trampoline setup function, Ajeet Singh, 2024/09/15
- [PATCH v6 08/17] bsd-user: Implement RISC-V sysarch system call emulation,
Ajeet Singh <=
- [PATCH v6 09/17] bsd-user: Add RISC-V thread setup and initialization support, Ajeet Singh, 2024/09/15
- [PATCH v6 10/17] bsd-user: Define RISC-V VM parameters and helper functions, Ajeet Singh, 2024/09/15
- [PATCH v6 11/17] bsd-user: Define RISC-V system call structures and constants, Ajeet Singh, 2024/09/15
- [PATCH v6 12/17] bsd-user: Add generic RISC-V64 target definitions, Ajeet Singh, 2024/09/15
- [PATCH v6 13/17] bsd-user: Define RISC-V signal handling structures and constants, Ajeet Singh, 2024/09/15
- [PATCH v6 14/17] bsd-user: Implement RISC-V signal trampoline setup functions, Ajeet Singh, 2024/09/15
- [PATCH v6 15/17] bsd-user: Implement 'get_mcontext' for RISC-V, Ajeet Singh, 2024/09/15
- [PATCH v6 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV, Ajeet Singh, 2024/09/15
- [PATCH v6 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files, Ajeet Singh, 2024/09/15
- Re: [PATCH v6 00/17] bsd-user: Comprehensive RISCV Support, Daniel Henrique Barboza, 2024/09/16