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[PULL v2 03/47] tests/qtest/bios-tables-test.c: Enable numamem testing f
From: |
Alistair Francis |
Subject: |
[PULL v2 03/47] tests/qtest/bios-tables-test.c: Enable numamem testing for RISC-V |
Date: |
Wed, 25 Sep 2024 08:17:04 +1000 |
From: Haibo Xu <haibo1.xu@intel.com>
Add ACPI SRAT table test case for RISC-V when NUMA was enabled.
Signed-off-by: Haibo Xu <haibo1.xu@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID:
<a6f7e1a4b20ff7eb199e94ca0c8aa2e6794ce5b2.1723172696.git.haibo1.xu@intel.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
tests/qtest/bios-tables-test.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 36e5c0adde..e79f3a03df 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1706,6 +1706,32 @@ static void test_acpi_microvm_ioapic2_tcg(void)
free_test_data(&data);
}
+static void test_acpi_riscv64_virt_tcg_numamem(void)
+{
+ test_data data = {
+ .machine = "virt",
+ .arch = "riscv64",
+ .tcg_only = true,
+ .uefi_fl1 = "pc-bios/edk2-riscv-code.fd",
+ .uefi_fl2 = "pc-bios/edk2-riscv-vars.fd",
+ .cd = "tests/data/uefi-boot-images/bios-tables-test.riscv64.iso.qcow2",
+ .ram_start = 0x80000000ULL,
+ .scan_len = 128ULL * 1024 * 1024,
+ };
+
+ data.variant = ".numamem";
+ /*
+ * RHCT will have ISA string encoded. To reduce the effort
+ * of updating expected AML file for any new default ISA extension,
+ * use the profile rva22s64.
+ */
+ test_acpi_one(" -cpu rva22s64"
+ " -object memory-backend-ram,id=ram0,size=128M"
+ " -numa node,memdev=ram0",
+ &data);
+ free_test_data(&data);
+}
+
static void test_acpi_aarch64_virt_tcg_numamem(void)
{
test_data data = {
@@ -2466,6 +2492,8 @@ int main(int argc, char *argv[])
} else if (strcmp(arch, "riscv64") == 0) {
if (has_tcg && qtest_has_device("virtio-blk-pci")) {
qtest_add_func("acpi/virt", test_acpi_riscv64_virt_tcg);
+ qtest_add_func("acpi/virt/numamem",
+ test_acpi_riscv64_virt_tcg_numamem);
}
}
ret = g_test_run();
--
2.46.1
- [PULL v2 00/47] riscv-to-apply queue, Alistair Francis, 2024/09/24
- [PULL v2 01/47] target/riscv: Add a property to set vl to ceil(AVL/2), Alistair Francis, 2024/09/24
- [PULL v2 02/47] tests/acpi: Add empty ACPI SRAT data file for RISC-V, Alistair Francis, 2024/09/24
- [PULL v2 03/47] tests/qtest/bios-tables-test.c: Enable numamem testing for RISC-V,
Alistair Francis <=
- [PULL v2 04/47] tests/acpi: Add expected ACPI SRAT AML file for RISC-V, Alistair Francis, 2024/09/24
- [PULL v2 05/47] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule, Alistair Francis, 2024/09/24
- [PULL v2 06/47] target/riscv: fix za64rs enabling, Alistair Francis, 2024/09/24
- [PULL v2 07/47] target: riscv: Enable Bit Manip for OpenTitan Ibex CPU, Alistair Francis, 2024/09/24
- [PULL v2 08/47] target/riscv/kvm: Fix the group bit setting of AIA, Alistair Francis, 2024/09/24
- [PULL v2 09/47] target/riscv: Stop timer with infinite timecmp, Alistair Francis, 2024/09/24
- [PULL v2 10/47] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension, Alistair Francis, 2024/09/24
- [PULL v2 11/47] util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc, Alistair Francis, 2024/09/24
- [PULL v2 12/47] target/riscv: Preliminary textra trigger CSR writting support, Alistair Francis, 2024/09/24
- [PULL v2 13/47] target/riscv: Add textra matching condition for the triggers, Alistair Francis, 2024/09/24