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[PULL v2 19/47] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotp
From: |
Alistair Francis |
Subject: |
[PULL v2 19/47] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug |
Date: |
Wed, 25 Sep 2024 08:17:20 +1000 |
From: Tomasz Jeznach <tjeznach@rivosinc.com>
Generate device tree entry for riscv-iommu PCI device, along with
mapping all PCI device identifiers to the single IOMMU device instance.
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240903201633.93182-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 33 ++++++++++++++++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index cef41c150a..63d553ac98 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -32,6 +32,7 @@
#include "hw/core/sysbus-fdt.h"
#include "target/riscv/pmu.h"
#include "hw/riscv/riscv_hart.h"
+#include "hw/riscv/iommu.h"
#include "hw/riscv/virt.h"
#include "hw/riscv/boot.h"
#include "hw/riscv/numa.h"
@@ -1032,6 +1033,30 @@ static void create_fdt_virtio_iommu(RISCVVirtState *s,
uint16_t bdf)
bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf);
}
+static void create_fdt_iommu(RISCVVirtState *s, uint16_t bdf)
+{
+ const char comp[] = "riscv,pci-iommu";
+ void *fdt = MACHINE(s)->fdt;
+ uint32_t iommu_phandle;
+ g_autofree char *iommu_node = NULL;
+ g_autofree char *pci_node = NULL;
+
+ pci_node = g_strdup_printf("/soc/pci@%lx",
+ (long) virt_memmap[VIRT_PCIE_ECAM].base);
+ iommu_node = g_strdup_printf("%s/iommu@%x", pci_node, bdf);
+ iommu_phandle = qemu_fdt_alloc_phandle(fdt);
+ qemu_fdt_add_subnode(fdt, iommu_node);
+
+ qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp));
+ qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1);
+ qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle);
+ qemu_fdt_setprop_cells(fdt, iommu_node, "reg",
+ bdf << 8, 0, 0, 0, 0);
+ qemu_fdt_setprop_cells(fdt, pci_node, "iommu-map",
+ 0, iommu_phandle, 0, bdf,
+ bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf);
+}
+
static void finalize_fdt(RISCVVirtState *s)
{
uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
@@ -1738,9 +1763,11 @@ static HotplugHandler
*virt_machine_get_hotplug_handler(MachineState *machine,
MachineClass *mc = MACHINE_GET_CLASS(machine);
if (device_is_dynamic_sysbus(mc, dev) ||
- object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
+ object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
+ object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) {
return HOTPLUG_HANDLER(machine);
}
+
return NULL;
}
@@ -1761,6 +1788,10 @@ static void virt_machine_device_plug_cb(HotplugHandler
*hotplug_dev,
if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
create_fdt_virtio_iommu(s, pci_get_bdf(PCI_DEVICE(dev)));
}
+
+ if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) {
+ create_fdt_iommu(s, pci_get_bdf(PCI_DEVICE(dev)));
+ }
}
static void virt_machine_class_init(ObjectClass *oc, void *data)
--
2.46.1
- [PULL v2 09/47] target/riscv: Stop timer with infinite timecmp, (continued)
- [PULL v2 09/47] target/riscv: Stop timer with infinite timecmp, Alistair Francis, 2024/09/24
- [PULL v2 10/47] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension, Alistair Francis, 2024/09/24
- [PULL v2 11/47] util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc, Alistair Francis, 2024/09/24
- [PULL v2 12/47] target/riscv: Preliminary textra trigger CSR writting support, Alistair Francis, 2024/09/24
- [PULL v2 13/47] target/riscv: Add textra matching condition for the triggers, Alistair Francis, 2024/09/24
- [PULL v2 14/47] exec/memtxattr: add process identifier to the transaction attributes, Alistair Francis, 2024/09/24
- [PULL v2 15/47] hw/riscv: add riscv-iommu-bits.h, Alistair Francis, 2024/09/24
- [PULL v2 17/47] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device, Alistair Francis, 2024/09/24
- [PULL v2 16/47] hw/riscv: add RISC-V IOMMU base emulation, Alistair Francis, 2024/09/24
- [PULL v2 18/47] hw/riscv: add riscv-iommu-pci reference device, Alistair Francis, 2024/09/24
- [PULL v2 19/47] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug,
Alistair Francis <=
- [PULL v2 20/47] test/qtest: add riscv-iommu-pci tests, Alistair Francis, 2024/09/24
- [PULL v2 21/47] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC), Alistair Francis, 2024/09/24
- [PULL v2 22/47] hw/riscv/riscv-iommu: add ATS support, Alistair Francis, 2024/09/24
- [PULL v2 23/47] hw/riscv/riscv-iommu: add DBG support, Alistair Francis, 2024/09/24
- [PULL v2 24/47] qtest/riscv-iommu-test: add init queues test, Alistair Francis, 2024/09/24
- [PULL v2 25/47] docs/specs: add riscv-iommu, Alistair Francis, 2024/09/24
- [PULL v2 26/47] hw/riscv: Respect firmware ELF entry point, Alistair Francis, 2024/09/24
- [PULL v2 27/47] target: riscv: Add Svvptc extension support, Alistair Francis, 2024/09/24
- [PULL v2 28/47] target/riscv32: Fix masking of physical address, Alistair Francis, 2024/09/24
- [PULL v2 29/47] target/riscv/cpu_helper: Fix linking problem with semihosting disabled, Alistair Francis, 2024/09/24