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[PATCH v2 5/8] target/riscv: Add Smdbltrp CSRs handling
From: |
Clément Léger |
Subject: |
[PATCH v2 5/8] target/riscv: Add Smdbltrp CSRs handling |
Date: |
Wed, 25 Sep 2024 13:58:03 +0200 |
Add `ext_smdbltrp`in RISCVCPUConfig and implement MSTATUS.MDT behavior.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_cfg.h | 1 +
target/riscv/csr.c | 15 +++++++++++++++
3 files changed, 17 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 5557a86348..62bab1bf55 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -561,6 +561,7 @@
#define MSTATUS_SDT 0x01000000
#define MSTATUS_GVA 0x4000000000ULL
#define MSTATUS_MPV 0x8000000000ULL
+#define MSTATUS_MDT 0x40000000000ULL /* Smdbltrp extension */
#define MSTATUS64_UXL 0x0000000300000000ULL
#define MSTATUS64_SXL 0x0000000C00000000ULL
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index dd804f95d4..4c4caa2b39 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -78,6 +78,7 @@ struct RISCVCPUConfig {
bool ext_sstc;
bool ext_smcntrpmf;
bool ext_ssdbltrp;
+ bool ext_smdbltrp;
bool ext_svadu;
bool ext_svinval;
bool ext_svnapot;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d8280ec956..cc1940447a 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1617,6 +1617,14 @@ static RISCVException write_mstatus(CPURISCVState *env,
int csrno,
}
}
+ if (riscv_cpu_cfg(env)->ext_smdbltrp) {
+ mask |= MSTATUS_MDT;
+ if ((val & MSTATUS_MDT) != 0) {
+ mstatus &= ~MSTATUS_MIE;
+ val &= ~MSTATUS_MIE;
+ }
+ }
+
if (xl != MXL_RV32 || env->debugger) {
if (riscv_has_ext(env, RVH)) {
mask |= MSTATUS_MPV | MSTATUS_GVA;
@@ -1655,6 +1663,13 @@ static RISCVException write_mstatush(CPURISCVState *env,
int csrno,
uint64_t valh = (uint64_t)val << 32;
uint64_t mask = riscv_has_ext(env, RVH) ? MSTATUS_MPV | MSTATUS_GVA : 0;
+ if (riscv_cpu_cfg(env)->ext_smdbltrp) {
+ mask |= MSTATUS_MDT;
+ if ((val & MSTATUS_MDT) != 0) {
+ env->mstatus &= ~MSTATUS_MIE;
+ val &= ~MSTATUS_MIE;
+ }
+ }
env->mstatus = (env->mstatus & ~mask) | (valh & mask);
return RISCV_EXCP_NONE;
--
2.45.2
- [PATCH v2 0/8] target/riscv: Add support for Smdbltrp and Ssdbltrp extensions, Clément Léger, 2024/09/25
- [PATCH v2 2/8] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior, Clément Léger, 2024/09/25
- [PATCH v2 1/8] target/riscv: Add Ssdbltrp CSRs handling, Clément Léger, 2024/09/25
- [PATCH v2 4/8] target/riscv: Add Ssdbltrp ISA extension enable switch, Clément Léger, 2024/09/25
- [PATCH v2 3/8] target/riscv: Implement Ssdbltrp exception handling, Clément Léger, 2024/09/25
- [PATCH v2 7/8] target/riscv: Implement Smdbltrp behavior, Clément Léger, 2024/09/25
- [PATCH v2 8/8] target/riscv: Add Smdbltrp ISA extension enable switch, Clément Léger, 2024/09/25
- [PATCH v2 5/8] target/riscv: Add Smdbltrp CSRs handling,
Clément Léger <=
- [PATCH v2 6/8] target/riscv: Implement Smdbltrp sret, mret and mnret behavior, Clément Léger, 2024/09/25