Re: [PATCH v3 5/6] hw/gpio/aspeed: Add AST2700 support

[Andrew Jeffery]

On Thu, 2024-09-26 at 15:45 +0800, Jamin Lin wrote:
> AST2700 integrates two set of Parallel GPIO Controller
> with maximum 212 control pins, which are 27 groups.
> (H, exclude pin: H7 H6 H5 H4)
> 
> In the previous design of ASPEED SOCs,
> one register is used for setting one function for one set which are 32 pins
> and 4 groups.
> ex: GPIO000 is used for setting data value for GPIO A, B, C and D in AST2600.
> ex: GPIO004 is used for setting direction for GPIO A, B, C and D in AST2600.
> 
> However, the register set have a significant change since AST2700.
> Each GPIO pin has their own individual control register. In other words, 
> users are able to
> set one GPIO pin’s direction, interrupt enable, input mask and so on
> in the same one register.
> 
> Currently, aspeed_gpio_read/aspeed_gpio_write callback functions
> are not compatible AST2700.
> Introduce new aspeed_gpio_2700_read/aspeed_gpio_2700_write callback functions
> and aspeed_gpio_2700_ops memory region operation for AST2700.
> Introduce a new ast2700 class to support AST2700.
> 
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>

Some of the wrapping in the commit message could be improved, but
otherwise:

Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>