Re: [PULL v2 00/47] riscv-to-apply queue

[Daniel Henrique Barboza]

On 9/30/24 9:10 AM, Ilya Leoshkevich wrote:
> On Sat, 2024-09-28 at 17:40 -0300, Daniel Henrique Barboza wrote:
> > On 9/28/24 8:34 AM, Peter Maydell wrote:
> > > On Tue, 24 Sept 2024 at 23:18, Alistair Francis
> > > <alistair23@gmail.com> wrote:
> > > > The following changes since commit
> > > > 01dc65a3bc262ab1bec8fe89775e9bbfa627becb:
> > > >
> > > >     Merge tag 'pull-target-arm-20240919' of
> > > > https://git.linaro.org/people/pmaydell/qemu-arm into staging
> > > > (2024-09-19 14:15:15 +0100)
> > > >
> > > > are available in the Git repository at:
> > > >
> > > >     https://github.com/alistair23/qemu.git tags/pull-riscv-to-
> > > > apply-20240925-1
> > > >
> > > > for you to fetch changes up to
> > > > 6bfa92c5757fe7a9580e1f6e065076777cae650f:
> > > >
> > > >     bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML
> > > > Files (2024-09-24 12:53:16 +1000)
> > > >
> > > > ----------------------------------------------------------------
> > > > RISC-V PR for 9.2
> > > >
> > > > * Add a property to set vl to ceil(AVL/2)
> > > > * Enable numamem testing for RISC-V
> > > > * Consider MISA bit choice in implied rule
> > > > * Fix the za64rs priv spec requirements
> > > > * Enable Bit Manip for OpenTitan Ibex CPU
> > > > * Fix the group bit setting of AIA with KVM
> > > > * Stop timer with infinite timecmp
> > > > * Add 'fcsr' register to QEMU log as a part of F extension
> > > > * Fix riscv64 build on musl libc
> > > > * Add preliminary textra trigger CSR functions
> > > > * RISC-V IOMMU support
> > > > * RISC-V bsd-user support
> > > > * Respect firmware ELF entry point
> > > > * Add Svvptc extension support
> > > > * Fix masking of rv32 physical address
> > > > * Fix linking problem with semihosting disabled
> > > > * Fix IMSIC interrupt state updates
> > >
> > > This fails the riscv qos-tests on s390x. My guess is that the new
> > > IOMMU support has endianness bugs and fails on bigendian hosts.
> > >
> > > https://gitlab.com/qemu-project/qemu/-/jobs/7942189143
> > >
> > > full test log (4MB) at
> > > https://qemu-project.gitlab.io/-/qemu/-/jobs/7942189143/artifacts/build/meson-logs/testlog.txt
> > >
> > > The assertion failure is
> > > ERROR:../tests/qtest/riscv-iommu-test.c:72:test_reg_reset:
> > > assertion
> > > failed (cap & RISCV_IOMMU_CAP_VERSION == 0x10): (0 == 16)
> >
> > The root cause is that the qtests I added aren't considering the
> > endianess of the
> > host. The RISC-V IOMMU is being implemented as LE only and all regs
> > are being
> > read/written in memory as LE. The qtest read/write helpers must take
> > the qtest
> > endianess into account. We make this type of handling in other qtest
> > archs like
> > ppc64.
> >
> > I have a fix for the tests but I'm unable to run the ubuntu-22.04-
> > s390x-all-system
> > job to verify it, even after setting Cirrus like Thomas taught me a
> > week ago. In
> > fact I have no 'ubuntu-22-*' jobs available to run.
> >
> > If there's a way to run these ubuntu s390x tests, let me know.
> > Otherwise I'm inclined
> > to remove the IOMMU qtests for now until I'm able to verify that
> > they'll work in a
> > BE host (I'll install a BE VM to verify).
>
> You can get a free s390x VM here:
>
> https://linuxone.cloud.marist.edu/#/register?flag=VM

Thanks! This was surprisingly easy to set up and run. Please send my best 
regards
to the LinuxOne Community Cloud team.

Peter, in fact there were some endianness problems in the code like you hinted
before. I fixed them up and the tests are now (apparently) passing. I'll clean
stuff up and see if I can send a new version of the whole series in the next
few days.


Thanks,

Daniel

> Best regards,
> Ilya
>
> [...]