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[PULL v3 30/35] bsd-user: Add generic RISC-V64 target definitions
From: |
Alistair Francis |
Subject: |
[PULL v3 30/35] bsd-user: Add generic RISC-V64 target definitions |
Date: |
Wed, 2 Oct 2024 15:50:43 +1000 |
From: Warner Losh <imp@bsdimp.com>
Added a generic definition for RISC-V64 target-specific details.
Implemented the 'regpairs_aligned' function,which returns 'false'
to indicate that register pairs are not aligned in the RISC-V64 ABI.
Signed-off-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240916155119.14610-13-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
bsd-user/riscv/target.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 bsd-user/riscv/target.h
diff --git a/bsd-user/riscv/target.h b/bsd-user/riscv/target.h
new file mode 100644
index 0000000000..036ddd185e
--- /dev/null
+++ b/bsd-user/riscv/target.h
@@ -0,0 +1,20 @@
+/*
+ * Riscv64 general target stuff that's common to all aarch details
+ *
+ * Copyright (c) 2022 M. Warner Losh <imp@bsdimp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef TARGET_H
+#define TARGET_H
+
+/*
+ * riscv64 ABI does not 'lump' the registers for 64-bit args.
+ */
+static inline bool regpairs_aligned(void *cpu_env)
+{
+ return false;
+}
+
+#endif /* TARGET_H */
--
2.46.2
- [PULL v3 20/35] bsd-user: Add RISC-V CPU execution loop and syscall handling, (continued)
- [PULL v3 20/35] bsd-user: Add RISC-V CPU execution loop and syscall handling, Alistair Francis, 2024/10/02
- [PULL v3 21/35] bsd-user: Implement RISC-V CPU register cloning and reset functions, Alistair Francis, 2024/10/02
- [PULL v3 22/35] bsd-user: Implement RISC-V TLS register setup, Alistair Francis, 2024/10/02
- [PULL v3 24/35] bsd-user: Define RISC-V register structures and register copying, Alistair Francis, 2024/10/02
- [PULL v3 23/35] bsd-user: Add RISC-V ELF definitions and hardware capability detection, Alistair Francis, 2024/10/02
- [PULL v3 26/35] bsd-user: Implement RISC-V sysarch system call emulation, Alistair Francis, 2024/10/02
- [PULL v3 25/35] bsd-user: Add RISC-V signal trampoline setup function, Alistair Francis, 2024/10/02
- [PULL v3 27/35] bsd-user: Add RISC-V thread setup and initialization support, Alistair Francis, 2024/10/02
- [PULL v3 28/35] bsd-user: Define RISC-V VM parameters and helper functions, Alistair Francis, 2024/10/02
- [PULL v3 29/35] bsd-user: Define RISC-V system call structures and constants, Alistair Francis, 2024/10/02
- [PULL v3 30/35] bsd-user: Add generic RISC-V64 target definitions,
Alistair Francis <=
- [PULL v3 31/35] bsd-user: Define RISC-V signal handling structures and constants, Alistair Francis, 2024/10/02
- [PULL v3 34/35] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV, Alistair Francis, 2024/10/02
- [PULL v3 33/35] bsd-user: Implement 'get_mcontext' for RISC-V, Alistair Francis, 2024/10/02
- [PULL v3 32/35] bsd-user: Implement RISC-V signal trampoline setup functions, Alistair Francis, 2024/10/02
- [PULL v3 35/35] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files, Alistair Francis, 2024/10/02
- Re: [PULL v3 00/35] riscv-to-apply queue, Peter Maydell, 2024/10/03