Re: [PATCH v7 7/8] target/riscv: Add max32 CPU for RV64 QEMU

[Alistair Francis]

On Thu, Sep 19, 2024 at 3:56 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
> We may need 32-bit max for RV64 QEMU. Thus we add these two CPUs
> for RV64 QEMU.
>
> The reason we don't expose them to RV32 QEMU is that we already have
> max cpu with the same configuration. Another reason is that we want
> to follow the RISC-V custom where addw instruction doesn't exist in
> RV32 CPU.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Suggested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu-qom.h |  1 +
>  target/riscv/cpu.c     | 12 +++++++-----
>  2 files changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 4464c0fd7a..62115375cd 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -30,6 +30,7 @@
>  #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
>
>  #define TYPE_RISCV_CPU_MAX              RISCV_CPU_TYPE_NAME("max")
> +#define TYPE_RISCV_CPU_MAX32            RISCV_CPU_TYPE_NAME("max32")
>  #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
>  #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
>  #define TYPE_RISCV_CPU_BASE128          RISCV_CPU_TYPE_NAME("x-rv128")
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 86ce15252a..baf8fba467 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -448,11 +448,9 @@ static void riscv_max_cpu_init(Object *obj)
>
>      env->priv_ver = PRIV_VERSION_LATEST;
>  #ifndef CONFIG_USER_ONLY
> -#ifdef TARGET_RISCV32
> -    set_satp_mode_max_supported(cpu, VM_1_10_SV32);
> -#else
> -    set_satp_mode_max_supported(cpu, VM_1_10_SV57);
> -#endif
> +    set_satp_mode_max_supported(RISCV_CPU(obj),
> +        riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
> +        VM_1_10_SV32 : VM_1_10_SV57);
>  #endif
>  }
>
> @@ -2945,6 +2943,10 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>      DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E,        MXL_RV32,  
> rv32e_bare_cpu_init),
>  #endif
>
> +#if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
> +    DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX32,     MXL_RV32,  
> riscv_max_cpu_init),
> +#endif
> +
>  #if defined(TARGET_RISCV64)
>      DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64,    MXL_RV64,  
> rv64_base_cpu_init),
>      DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64,  
> rv64_sifive_e_cpu_init),
> --
> 2.43.0
>
>