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[PULL 09/24] tcg/riscv: Accept constant first argument to sub_vec
From: |
Richard Henderson |
Subject: |
[PULL 09/24] tcg/riscv: Accept constant first argument to sub_vec |
Date: |
Tue, 22 Oct 2024 20:34:17 -0700 |
Use vrsub.vi to subtract from a constant.
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target-con-set.h | 1 +
tcg/riscv/tcg-target.c.inc | 8 ++++++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h
index 97e6ecdb0f..d8ce5414f5 100644
--- a/tcg/riscv/tcg-target-con-set.h
+++ b/tcg/riscv/tcg-target-con-set.h
@@ -25,6 +25,7 @@ C_O0_I2(v, r)
C_O1_I1(v, r)
C_O1_I1(v, v)
C_O1_I2(v, v, v)
+C_O1_I2(v, vK, v)
C_O1_I2(v, v, vK)
C_O1_I2(v, v, vL)
C_O1_I4(v, v, vL, vK, vK)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index ce8d6d0293..1ce2f291d3 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -2350,7 +2350,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_sub_vec:
set_vtype_len_sew(s, type, vece);
- tcg_out_opc_vv(s, OPC_VSUB_VV, a0, a1, a2);
+ if (const_args[1]) {
+ tcg_out_opc_vi(s, OPC_VRSUB_VI, a0, a2, a1);
+ } else {
+ tcg_out_opc_vv(s, OPC_VSUB_VV, a0, a1, a2);
+ }
break;
case INDEX_op_and_vec:
set_vtype_len(s, type);
@@ -2565,7 +2569,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode
op)
case INDEX_op_xor_vec:
return C_O1_I2(v, v, vK);
case INDEX_op_sub_vec:
- return C_O1_I2(v, v, v);
+ return C_O1_I2(v, vK, v);
case INDEX_op_cmp_vec:
return C_O1_I2(v, v, vL);
case INDEX_op_cmpsel_vec:
--
2.43.0
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- [PULL 19/24] target/i386: Remove ra parameter from ptw_translate, Richard Henderson, 2024/10/22
- [PULL 15/24] tcg/ppc: Fix tcg_out_rlw_rc, Richard Henderson, 2024/10/22
- [PULL 10/24] tcg/riscv: Implement vector sat/mul ops, Richard Henderson, 2024/10/22
- [PULL 14/24] tcg/riscv: Enable native vector support for TCG host, Richard Henderson, 2024/10/22
- [PULL 02/24] disas/riscv: Fix vsetivli disassembly, Richard Henderson, 2024/10/22
- [PULL 06/24] tcg/riscv: Add support for basic vector opcodes, Richard Henderson, 2024/10/22
- [PULL 12/24] tcg/riscv: Implement vector shi/s/v ops, Richard Henderson, 2024/10/22
- [PULL 08/24] tcg/riscv: Implement vector neg ops, Richard Henderson, 2024/10/22
- [PULL 09/24] tcg/riscv: Accept constant first argument to sub_vec,
Richard Henderson <=
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- [PULL 16/24] include/exec: Improve probe_access_full{, _mmu} documentation, Richard Henderson, 2024/10/22
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- [PULL 21/24] linux-user/ppc: Fix sigmask endianness issue in sigreturn, Richard Henderson, 2024/10/22
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