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[PATCH v2 02/54] accel/tcg: Split out tlbfast_flush_locked
From: |
Richard Henderson |
Subject: |
[PATCH v2 02/54] accel/tcg: Split out tlbfast_flush_locked |
Date: |
Thu, 14 Nov 2024 08:00:38 -0800 |
We will have a need to flush only the "fast" portion
of the tlb, allowing re-fill from the "full" portion.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cputlb.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index b76a4eac4e..c1838412e8 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -284,13 +284,18 @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc,
CPUTLBDescFast *fast,
}
}
-static void tlb_mmu_flush_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast)
+static void tlbfast_flush_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast)
{
desc->n_used_entries = 0;
+ memset(fast->table, -1, sizeof_tlb(fast));
+}
+
+static void tlb_mmu_flush_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast)
+{
+ tlbfast_flush_locked(desc, fast);
desc->large_page_addr = -1;
desc->large_page_mask = -1;
desc->vindex = 0;
- memset(fast->table, -1, sizeof_tlb(fast));
memset(desc->vtable, -1, sizeof(desc->vtable));
}
--
2.43.0
- [PATCH for-10.0 v2 00/54] accel/tcg: Convert victim tlb to IntervalTree, Richard Henderson, 2024/11/14
- [PATCH v2 01/54] util/interval-tree: Introduce interval_tree_free_nodes, Richard Henderson, 2024/11/14
- [PATCH v2 05/54] accel/tcg: Fix flags usage in mmu_lookup1, atomic_mmu_lookup, Richard Henderson, 2024/11/14
- [PATCH v2 03/54] accel/tcg: Split out tlbfast_{index,entry}, Richard Henderson, 2024/11/14
- [PATCH v2 02/54] accel/tcg: Split out tlbfast_flush_locked,
Richard Henderson <=
- [PATCH v2 06/54] accel/tcg: Assert non-zero length in tlb_flush_range_by_mmuidx*, Richard Henderson, 2024/11/14
- [PATCH v2 04/54] accel/tcg: Split out tlbfast_flush_range_locked, Richard Henderson, 2024/11/14
- [PATCH v2 08/54] accel/tcg: Flush entire tlb when a masked range wraps, Richard Henderson, 2024/11/14
- [PATCH v2 09/54] accel/tcg: Add IntervalTreeRoot to CPUTLBDesc, Richard Henderson, 2024/11/14
- [PATCH v2 07/54] accel/tcg: Assert bits in range in tlb_flush_range_by_mmuidx*, Richard Henderson, 2024/11/14