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[PATCH v2 12/54] accel/tcg: Remove IntervalTree entries in tlb_flush_ran
From: |
Richard Henderson |
Subject: |
[PATCH v2 12/54] accel/tcg: Remove IntervalTree entries in tlb_flush_range_locked |
Date: |
Thu, 14 Nov 2024 08:00:48 -0800 |
Flush a masked range of pages from the IntervalTree cache.
When the mask is not used there is a redundant comparison,
but that is better than duplicating code at this point.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cputlb.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index d532d69083..e2c855f147 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -311,6 +311,13 @@ static CPUTLBEntryTree *tlbtree_lookup_range(CPUTLBDesc
*desc, vaddr s, vaddr l)
return i ? container_of(i, CPUTLBEntryTree, itree) : NULL;
}
+static CPUTLBEntryTree *tlbtree_lookup_range_next(CPUTLBEntryTree *prev,
+ vaddr s, vaddr l)
+{
+ IntervalTreeNode *i = interval_tree_iter_next(&prev->itree, s, l);
+ return i ? container_of(i, CPUTLBEntryTree, itree) : NULL;
+}
+
static CPUTLBEntryTree *tlbtree_lookup_addr(CPUTLBDesc *desc, vaddr addr)
{
return tlbtree_lookup_range(desc, addr, addr);
@@ -739,6 +746,8 @@ static void tlb_flush_range_locked(CPUState *cpu, int midx,
CPUTLBDesc *d = &cpu->neg.tlb.d[midx];
CPUTLBDescFast *f = &cpu->neg.tlb.f[midx];
vaddr mask = MAKE_64BIT_MASK(0, bits);
+ CPUTLBEntryTree *node;
+ vaddr addr_mask, last_mask, last_imask;
/*
* Check if we need to flush due to large pages.
@@ -759,6 +768,22 @@ static void tlb_flush_range_locked(CPUState *cpu, int midx,
vaddr page = addr + i;
tlb_flush_vtlb_page_mask_locked(cpu, midx, page, mask);
}
+
+ addr_mask = addr & mask;
+ last_mask = addr_mask + len - 1;
+ last_imask = last_mask | ~mask;
+ node = tlbtree_lookup_range(d, addr_mask, last_imask);
+ while (node) {
+ CPUTLBEntryTree *next =
+ tlbtree_lookup_range_next(node, addr_mask, last_imask);
+ vaddr page_mask = node->itree.start & mask;
+
+ if (page_mask >= addr_mask && page_mask < last_mask) {
+ interval_tree_remove(&node->itree, &d->iroot);
+ g_free(node);
+ }
+ node = next;
+ }
}
typedef struct {
--
2.43.0
- Re: [PATCH v2 02/54] accel/tcg: Split out tlbfast_flush_locked, (continued)
- [PATCH v2 06/54] accel/tcg: Assert non-zero length in tlb_flush_range_by_mmuidx*, Richard Henderson, 2024/11/14
- [PATCH v2 04/54] accel/tcg: Split out tlbfast_flush_range_locked, Richard Henderson, 2024/11/14
- [PATCH v2 08/54] accel/tcg: Flush entire tlb when a masked range wraps, Richard Henderson, 2024/11/14
- [PATCH v2 09/54] accel/tcg: Add IntervalTreeRoot to CPUTLBDesc, Richard Henderson, 2024/11/14
- [PATCH v2 07/54] accel/tcg: Assert bits in range in tlb_flush_range_by_mmuidx*, Richard Henderson, 2024/11/14
- [PATCH v2 12/54] accel/tcg: Remove IntervalTree entries in tlb_flush_range_locked,
Richard Henderson <=
- [PATCH v2 11/54] accel/tcg: Remove IntervalTree entry in tlb_flush_page_locked, Richard Henderson, 2024/11/14
- [PATCH v2 10/54] accel/tcg: Populate IntervalTree in tlb_set_page_full, Richard Henderson, 2024/11/14
- [PATCH v2 13/54] accel/tcg: Process IntervalTree entries in tlb_reset_dirty, Richard Henderson, 2024/11/14
- [PATCH v2 24/54] accel/tcg: Preserve tlb flags in tlb_set_compare, Richard Henderson, 2024/11/14
- [PATCH v2 25/54] accel/tcg: Return CPUTLBEntryFull not pointer in probe_access_full_mmu, Richard Henderson, 2024/11/14