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[PATCH v4 1/6] target/riscv: Add svukte extension capability variable
From: |
Fea.Wang |
Subject: |
[PATCH v4 1/6] target/riscv: Add svukte extension capability variable |
Date: |
Wed, 20 Nov 2024 15:48:49 +0800 |
Refer to the draft of svukte extension from:
https://github.com/riscv/riscv-isa-manual/pull/1564
Svukte provides a means to make user-mode accesses to supervisor memory
raise page faults in constant time, mitigating attacks that attempt to
discover the supervisor software's address-space layout.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 59d6fc445d..d8771ca641 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -84,6 +84,7 @@ struct RISCVCPUConfig {
bool ext_svnapot;
bool ext_svpbmt;
bool ext_svvptc;
+ bool ext_svukte;
bool ext_zdinx;
bool ext_zaamo;
bool ext_zacas;
--
2.34.1
- [PATCH v4 0/6] Introduce svukte ISA extension, Fea.Wang, 2024/11/20
- [PATCH v4 1/6] target/riscv: Add svukte extension capability variable,
Fea.Wang <=
- [PATCH v4 2/6] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled, Fea.Wang, 2024/11/20
- [PATCH v4 3/6] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled, Fea.Wang, 2024/11/20
- [PATCH v4 6/6] target/riscv: Check svukte is not enabled in RV32, Fea.Wang, 2024/11/20
- [PATCH v4 4/6] target/riscv: Check memory access to meet svukte rule, Fea.Wang, 2024/11/20
- [PATCH v4 5/6] target/riscv: Expose svukte ISA extension, Fea.Wang, 2024/11/20