[PATCH 1/1] pcie-root-port: Fast PCIe root ports for new machine

[Gao,Shiyuan]

> Some hardware devices now support PCIe 5.0, so change the default
> speed of the PCIe root port on new machine types.
>
> For passthrough Nvidia H20, this will be able to increase the h2d/d2h
> bandwidth ~17%.
>
> Origin:
> [CUDA Bandwidth Test] - Starting...
> Running on...
>
> Device 0: NVIDIA H20
> Quick Mode
>
> Host to Device Bandwidth, 1 Device(s)
> PINNED Memory Transfers
>    Transfer Size (Bytes)    Bandwidth(MB/s)
>    33554432            45915.4
>
> Device to Host Bandwidth, 1 Device(s)
> PINNED Memory Transfers
>    Transfer Size (Bytes)    Bandwidth(MB/s)
>    33554432            45980.3
>
> Device to Device Bandwidth, 1 Device(s)
> PINNED Memory Transfers
>    Transfer Size (Bytes)    Bandwidth(MB/s)
>    33554432            1842886.8
>
> Result = PASS
>
> With this patch:
> [CUDA Bandwidth Test] - Starting...
> Running on...
>
> Device 0: NVIDIA H20
> Quick Mode
>
> Host to Device Bandwidth, 1 Device(s)
> PINNED Memory Transfers
>    Transfer Size (Bytes)      Bandwidth(MB/s)
>    33554432                   53682.0
>
> Device to Host Bandwidth, 1 Device(s)
> PINNED Memory Transfers
>    Transfer Size (Bytes)      Bandwidth(MB/s)
>    33554432                   53766.0
>
> Device to Device Bandwidth, 1 Device(s)
> PINNED Memory Transfers
>    Transfer Size (Bytes)      Bandwidth(MB/s)
>    33554432                   1842555.1
>
> Result = PASS
>
> Signed-off-by: Gao Shiyuan <gaoshiyuan@baidu.com>
> ---
> hw/core/machine.c                  | 1 +
> hw/pci-bridge/gen_pcie_root_port.c | 2 +-
> 2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/core/machine.c b/hw/core/machine.c
> index a35c4a8fae..afef55626d 100644
> --- a/hw/core/machine.c
> +++ b/hw/core/machine.c
> @@ -38,6 +38,7 @@
>
> GlobalProperty hw_compat_9_1[] = {
>      { TYPE_PCI_DEVICE, "x-pcie-ext-tag", "false" },
> +    { "pcie-root-port", "x-speed", "16" },
> };
> const size_t hw_compat_9_1_len = G_N_ELEMENTS(hw_compat_9_1);
>
> diff --git a/hw/pci-bridge/gen_pcie_root_port.c 
> b/hw/pci-bridge/gen_pcie_root_port.c
> index 784507c826..c24ce1f2d1 100644
> --- a/hw/pci-bridge/gen_pcie_root_port.c
> +++ b/hw/pci-bridge/gen_pcie_root_port.c
> @@ -142,7 +142,7 @@ static Property gen_rp_props[] = {
>      DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort,
>                       res_reserve.mem_pref_64, -1),
>      DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,
> -                                speed, PCIE_LINK_SPEED_16),
> +                                speed, PCIE_LINK_SPEED_32),
>      DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
>                                  width, PCIE_LINK_WIDTH_32),
>      DEFINE_PROP_END_OF_LIST()
> --
> 2.34.1

Ping.