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[PATCH v4 11/11] target/riscv: Add configuration for S[m|s]csrind, Smcde
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From: |
Atish Patra |
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Subject: |
[PATCH v4 11/11] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg |
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Date: |
Tue, 03 Dec 2024 15:14:49 -0800 |
Add configuration options so that they can be enabled/disabld from
qemu commandline.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 410ca2e3a666..2a4f285a974f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1477,6 +1477,10 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false),
+ MULTI_EXT_CFG_BOOL("smcsrind", ext_smcsrind, false),
+ MULTI_EXT_CFG_BOOL("smcdeleg", ext_smcdeleg, false),
+ MULTI_EXT_CFG_BOOL("sscsrind", ext_sscsrind, false),
+ MULTI_EXT_CFG_BOOL("ssccfg", ext_ssccfg, false),
MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true),
MULTI_EXT_CFG_BOOL("zicfilp", ext_zicfilp, false),
MULTI_EXT_CFG_BOOL("zicfiss", ext_zicfiss, false),
--
2.34.1
- [PATCH v4 03/11] target/riscv: Enable S*stateen bits for AIA, (continued)
- [PATCH v4 03/11] target/riscv: Enable S*stateen bits for AIA, Atish Patra, 2024/12/03
- [PATCH v4 02/11] target/riscv: Decouple AIA processing from xiselect and xireg, Atish Patra, 2024/12/03
- [PATCH v4 04/11] target/riscv: Support generic CSR indirect access, Atish Patra, 2024/12/03
- [PATCH v4 05/11] target/riscv: Add properties for counter delegation ISA extensions, Atish Patra, 2024/12/03
- [PATCH v4 06/11] target/riscv: Add counter delegation definitions, Atish Patra, 2024/12/03
- [PATCH v4 07/11] target/riscv: Add select value range check for counter delegation, Atish Patra, 2024/12/03
- [PATCH v4 10/11] target/riscv: Add implied rule for counter delegation extensions, Atish Patra, 2024/12/03
- [PATCH v4 08/11] target/riscv: Add counter delegation/configuration support, Atish Patra, 2024/12/03
- [PATCH v4 11/11] target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg,
Atish Patra <=
- [PATCH v4 09/11] target/riscv: Invoke pmu init after feature enable, Atish Patra, 2024/12/03