Re: [PATCH for-10.0 9/9] target/riscv/tcg: add sha

[Alistair Francis]

On Thu, Nov 14, 2024 at 2:19 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> 'sha' is the augmented hypervisor extension, defined in RVA22 as a set of
> the following extensions:
>
> - RVH
> - Ssstateen
> - Shcounterenw (always present)
> - Shvstvala (always present)
> - Shtvala (always present)
> - Shvstvecd (always present)
> - Shvsatpa (always present)
> - Shgatpa (always present)
>
> We can claim support for 'sha' by checking if we have RVH and ssstateen.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c         | 2 ++
>  target/riscv/cpu_cfg.h     | 1 +
>  target/riscv/tcg/tcg-cpu.c | 8 ++++++++
>  3 files changed, 11 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index fff7010647..a8b8c9e775 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -184,6 +184,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
>      ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
>      ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
> +    ISA_EXT_DATA_ENTRY(sha, PRIV_VERSION_1_12_0, ext_sha),
>      ISA_EXT_DATA_ENTRY(shgatpa, PRIV_VERSION_1_12_0, has_priv_1_12),
>      ISA_EXT_DATA_ENTRY(shtvala, PRIV_VERSION_1_12_0, has_priv_1_12),
>      ISA_EXT_DATA_ENTRY(shvsatpa, PRIV_VERSION_1_12_0, has_priv_1_12),
> @@ -1615,6 +1616,7 @@ const RISCVCPUMultiExtConfig 
> riscv_cpu_experimental_exts[] = {
>  const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
>      MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
>      MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true),
> +    MULTI_EXT_CFG_BOOL("sha", ext_sha, true),
>
>      DEFINE_PROP_END_OF_LIST(),
>  };
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index c7bf455614..7c60a5becb 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -140,6 +140,7 @@ struct RISCVCPUConfig {
>      bool ext_svade;
>      bool ext_zic64b;
>      bool ext_ssstateen;
> +    bool ext_sha;
>
>      /*
>       * Always 'true' booleans for named features
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 0b9be2b0d3..b06638cca4 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -210,6 +210,11 @@ static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, 
> uint32_t feat_offset)
>          cpu->cfg.cbop_blocksize = 64;
>          cpu->cfg.cboz_blocksize = 64;
>          break;
> +    case CPU_CFG_OFFSET(ext_sha):
> +        if (!cpu_misa_ext_is_user_set(RVH)) {
> +            riscv_cpu_write_misa_bit(cpu, RVH, true);
> +        }
> +        /* fallthrough */
>      case CPU_CFG_OFFSET(ext_ssstateen):
>          cpu->cfg.ext_smstateen = true;
>          break;
> @@ -350,6 +355,9 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)
>                            cpu->cfg.cboz_blocksize == 64;
>
>      cpu->cfg.ext_ssstateen = cpu->cfg.ext_smstateen;
> +
> +    cpu->cfg.ext_sha = riscv_has_ext(&cpu->env, RVH) &&
> +                       cpu->cfg.ext_ssstateen;
>  }
>
>  static void riscv_cpu_validate_g(RISCVCPU *cpu)
> --
> 2.47.0
>
>