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[PATCH v3 4/8] i386: Add RDT device interface through MSRs
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From: |
Hendrik Wuethrich |
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Subject: |
[PATCH v3 4/8] i386: Add RDT device interface through MSRs |
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Date: |
Wed, 4 Dec 2024 08:48:33 +0000 |
From: Hendrik Wüthrich <whendrik@google.com>
Implement rdmsr and wrmsr for the following MSRs:
* MSR_IA32_PQR_ASSOC
* MSR_IA32_QM_EVTSEL
* MSR_IA32_QM_CTR
* IA32_L3_QOS_Mask_n
* IA32_L2_QOS_Mask_n
* IA32_L2_QoS_Ext_BW_Thrtl_n
This allows for the guest to call RDT-internal functions to
associate an RMID with a CLOSID / set an active RMID for
monitoring, read monitoring data, and set classes of service.
Signed-off-by: Hendrik Wüthrich <whendrik@google.com>
---
hw/i386/rdt.c | 22 ++++----
include/hw/i386/rdt.h | 6 +-
target/i386/cpu.h | 14 +++++
target/i386/tcg/sysemu/misc_helper.c | 84 ++++++++++++++++++++++++++++
4 files changed, 113 insertions(+), 13 deletions(-)
diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c
index 19fea8999a..f295273aec 100644
--- a/hw/i386/rdt.c
+++ b/hw/i386/rdt.c
@@ -77,6 +77,10 @@ struct RDTState {
struct RDTStateClass {
};
+uint32_t rdt_get_cpuid_10_1_edx_cos_max(void) { return RDT_MAX_L3_MASK_COUNT; }
+uint32_t rdt_get_cpuid_10_2_edx_cos_max(void) { return RDT_MAX_L2_MASK_COUNT; }
+uint32_t rdt_get_cpuid_10_3_edx_cos_max(void) { return
RDT_MAX_MBA_THRTL_COUNT; }
+
bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc) {
X86CPU *cpu = X86_CPU(current_cpu);
RDTStatePerCore *rdt = cpu->rdt;
@@ -86,7 +90,7 @@ bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc) {
uint32_t rmid = msr_ia32_pqr_assoc & 0xffff;
if (cos_id > RDT_MAX_L3_MASK_COUNT || cos_id > RDT_MAX_L2_MASK_COUNT ||
- cos_id > RDT_MAX_MBA_THRTL_COUNT || rmid > rdt_max_rmid(rdt)) {
+ cos_id > RDT_MAX_MBA_THRTL_COUNT || rmid > rdt_max_rmid(rdt)) {
return false;
}
@@ -104,8 +108,7 @@ uint32_t rdt_read_l3_mask(uint32_t pos)
X86CPU *cpu = X86_CPU(current_cpu);
RDTStatePerCore *rdt = cpu->rdt;
- uint32_t val = rdt->rdtstate->msr_L3_ia32_mask_n[pos];
- return val;
+ return rdt->rdtstate->msr_L3_ia32_mask_n[pos];
}
uint32_t rdt_read_l2_mask(uint32_t pos)
@@ -113,8 +116,7 @@ uint32_t rdt_read_l2_mask(uint32_t pos)
X86CPU *cpu = X86_CPU(current_cpu);
RDTStatePerCore *rdt = cpu->rdt;
- uint32_t val = rdt->rdtstate->msr_L2_ia32_mask_n[pos];
- return val;
+ return rdt->rdtstate->msr_L2_ia32_mask_n[pos];
}
uint32_t rdt_read_mba_thrtl(uint32_t pos)
@@ -122,8 +124,7 @@ uint32_t rdt_read_mba_thrtl(uint32_t pos)
X86CPU *cpu = X86_CPU(current_cpu);
RDTStatePerCore *rdt = cpu->rdt;
- uint32_t val = rdt->rdtstate->ia32_L2_qos_ext_bw_thrtl_n[pos];
- return val;
+ return rdt->rdtstate->ia32_L2_qos_ext_bw_thrtl_n[pos];
}
void rdt_write_msr_l3_mask(uint32_t pos, uint32_t val) {
@@ -153,7 +154,8 @@ uint32_t rdt_max_rmid(RDTStatePerCore *rdt)
return rdtdev->rmids - 1;
}
-uint64_t rdt_read_event_count(RDTStatePerCore *rdtInstance, uint32_t rmid,
uint32_t event_id)
+uint64_t rdt_read_event_count(RDTStatePerCore *rdtInstance,
+ uint32_t rmid, uint32_t event_id)
{
CPUState *cs;
RDTMonitor *mon;
@@ -181,13 +183,10 @@ uint64_t rdt_read_event_count(RDTStatePerCore
*rdtInstance, uint32_t rmid, uint3
switch (event_id) {
case RDT_EVENT_L3_OCCUPANCY:
return count_l3 == 0 ? QM_CTR_UNAVAILABLE : count_l3;
- break;
case RDT_EVENT_L3_REMOTE_BW:
return count_remote == 0 ? QM_CTR_UNAVAILABLE : count_remote;
- break;
case RDT_EVENT_L3_LOCAL_BW:
return count_local == 0 ? QM_CTR_UNAVAILABLE : count_local;
- break;
default:
return QM_CTR_ERROR;
}
@@ -247,4 +246,3 @@ static void rdt_class_init(ObjectClass *klass, void *data)
device_class_set_props(dc, rdt_properties);
}
-
diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h
index 875142bad8..ec82a149f2 100644
--- a/include/hw/i386/rdt.h
+++ b/include/hw/i386/rdt.h
@@ -25,7 +25,10 @@ typedef struct RDTStatePerCore RDTStatePerCore;
typedef struct RDTMonitor RDTMonitor;
typedef struct RDTAllocation RDTAllocation;
-#endif
+uint32_t rdt_get_cpuid_10_1_edx_cos_max(void);
+uint32_t rdt_get_cpuid_10_2_edx_cos_max(void);
+uint32_t rdt_get_cpuid_10_3_edx_cos_max(void);
+
bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc);
void rdt_write_msr_l3_mask(uint32_t pos, uint32_t val);
@@ -39,3 +42,4 @@ uint32_t rdt_read_mba_thrtl(uint32_t pos);
uint64_t rdt_read_event_count(RDTStatePerCore *rdt, uint32_t rmid, uint32_t
event_id);
uint32_t rdt_max_rmid(RDTStatePerCore *rdt);
+#endif
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index a2941f98eb..d7d5ad37fd 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -574,6 +574,17 @@ typedef enum X86Seg {
#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
#define MSR_IA32_VMX_VMFUNC 0x00000491
+#define MSR_IA32_QM_EVTSEL 0x0c8d
+#define MSR_IA32_QM_CTR 0x0c8e
+#define MSR_IA32_PQR_ASSOC 0x0c8f
+
+#define MSR_IA32_L3_CBM_BASE 0x0c90
+#define MSR_IA32_L3_MASKS_END 0x0d0f
+#define MSR_IA32_L2_CBM_BASE 0x0d10
+#define MSR_IA32_L2_CBM_END 0x0d4f
+#define MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE 0xd50
+#define MSR_IA32_L2_QOS_Ext_BW_Thrtl_END 0xd8f
+
#define MSR_APIC_START 0x00000800
#define MSR_APIC_END 0x000008ff
@@ -1778,6 +1789,9 @@ typedef struct CPUArchState {
uint64_t msr_ia32_feature_control;
uint64_t msr_ia32_sgxlepubkeyhash[4];
+ uint64_t msr_ia32_qm_evtsel;
+ uint64_t msr_ia32_pqr_assoc;
+
uint64_t msr_fixed_ctr_ctrl;
uint64_t msr_global_ctrl;
uint64_t msr_global_status;
diff --git a/target/i386/tcg/sysemu/misc_helper.c
b/target/i386/tcg/sysemu/misc_helper.c
index 094aa56a20..707cd3dc81 100644
--- a/target/i386/tcg/sysemu/misc_helper.c
+++ b/target/i386/tcg/sysemu/misc_helper.c
@@ -25,6 +25,7 @@
#include "exec/address-spaces.h"
#include "exec/exec-all.h"
#include "tcg/helper-tcg.h"
+#include "hw/i386/rdt.h"
#include "hw/i386/apic.h"
void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
@@ -293,6 +294,47 @@ void helper_wrmsr(CPUX86State *env)
env->msr_bndcfgs = val;
cpu_sync_bndcs_hflags(env);
break;
+ case MSR_IA32_QM_EVTSEL:
+ env->msr_ia32_qm_evtsel = val;
+ break;
+ case MSR_IA32_PQR_ASSOC:
+ {
+ env->msr_ia32_pqr_assoc = val;
+
+ if (!rdt_associate_rmid_cos(val))
+ goto error;
+ break;
+ }
+ case MSR_IA32_L3_CBM_BASE ... MSR_IA32_L3_MASKS_END:
+ {
+ uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L3_CBM_BASE;
+
+ if (pos > rdt_get_cpuid_10_1_edx_cos_max()) {
+ goto error;
+ }
+ rdt_write_msr_l3_mask(pos, val);
+ break;
+ }
+ case MSR_IA32_L2_CBM_BASE ... MSR_IA32_L2_CBM_END:
+ {
+ uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_CBM_BASE;
+
+ if (pos > rdt_get_cpuid_10_2_edx_cos_max()) {
+ goto error;
+ }
+ rdt_write_msr_l2_mask(pos, val);
+ break;
+ }
+ case MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE ...
MSR_IA32_L2_QOS_Ext_BW_Thrtl_END:
+ {
+ uint32_t pos = (uint32_t)env->regs[R_ECX] -
MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE;
+
+ if (pos > rdt_get_cpuid_10_3_edx_cos_max()) {
+ goto error;
+ }
+ rdt_write_mba_thrtl(pos, val);
+ break;
+ }
case MSR_APIC_START ... MSR_APIC_END: {
int ret;
int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START;
@@ -472,6 +514,47 @@ void helper_rdmsr(CPUX86State *env)
val = (cs->nr_threads * cs->nr_cores) | (cs->nr_cores << 16);
break;
}
+ case MSR_IA32_QM_CTR:
+ val = rdt_read_event_count(x86_cpu->rdt,
+ (env->msr_ia32_qm_evtsel >> 32) & 0xff,
+ env->msr_ia32_qm_evtsel & 0xff);
+ break;
+ case MSR_IA32_QM_EVTSEL:
+ val = env->msr_ia32_qm_evtsel;
+ break;
+ case MSR_IA32_PQR_ASSOC:
+ val = env->msr_ia32_pqr_assoc;
+ break;
+ case MSR_IA32_L3_CBM_BASE ... MSR_IA32_L3_MASKS_END:
+ {
+ uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L3_CBM_BASE;
+
+ if (pos >= rdt_get_cpuid_10_1_edx_cos_max()) {
+ raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
+ }
+ val = rdt_read_l3_mask(pos);
+ break;
+ }
+ case MSR_IA32_L2_CBM_BASE ... MSR_IA32_L2_CBM_END:
+ {
+ uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_CBM_BASE;
+
+ if (pos >= rdt_get_cpuid_10_2_edx_cos_max()) {
+ raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
+ }
+ val = rdt_read_l2_mask(pos);
+ break;
+ }
+ case MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE ...
MSR_IA32_L2_QOS_Ext_BW_Thrtl_END:
+ {
+ uint32_t pos = (uint32_t)env->regs[R_ECX] -
MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE;
+
+ if (pos >= rdt_get_cpuid_10_3_edx_cos_max()) {
+ raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
+ }
+ val = rdt_read_mba_thrtl(pos);
+ break;
+ }
case MSR_APIC_START ... MSR_APIC_END: {
int ret;
int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START;
@@ -499,6 +582,7 @@ void helper_rdmsr(CPUX86State *env)
}
env->regs[R_EAX] = (uint32_t)(val);
env->regs[R_EDX] = (uint32_t)(val >> 32);
+ return;
}
void helper_flush_page(CPUX86State *env, target_ulong addr)
--
2.47.0.338.g60cca15819-goog
- [PATCH v3 0/8] The aim of this patch series is to emulate Intel RDT features in order to make testing of the linux Resctrl subsystem possible with Qemu., Hendrik Wuethrich, 2024/12/04
- [PATCH v3 1/8] i386: Add Intel RDT device and State to config., Hendrik Wuethrich, 2024/12/04
- [PATCH v3 2/8] i386: Add init and realize funciontality for RDT device., Hendrik Wuethrich, 2024/12/04
- [PATCH v3 3/8] i386: Add RDT functionality, Hendrik Wuethrich, 2024/12/04
- [PATCH v3 4/8] i386: Add RDT device interface through MSRs,
Hendrik Wuethrich <=
- [PATCH v3 6/8] i386: Add RDT feature flags., Hendrik Wuethrich, 2024/12/04
- [PATCH v3 5/8] i386: Add CPUID enumeration for RDT, Hendrik Wuethrich, 2024/12/04
- [PATCH v3 7/8] i386/cpu: Adjust CPUID level for RDT features, Hendrik Wuethrich, 2024/12/04
- [PATCH v3 8/8] i386/cpu: Adjust level for RDT on full_cpuid_auto_level, Hendrik Wuethrich, 2024/12/04