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[PATCH RFCv2 11/20] arm/cpu: Store id_dfr0/1 into the idregs array
|
From: |
Cornelia Huck |
|
Subject: |
[PATCH RFCv2 11/20] arm/cpu: Store id_dfr0/1 into the idregs array |
|
Date: |
Fri, 6 Dec 2024 12:22:04 +0100 |
From: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
hw/intc/armv7m_nvic.c | 2 +-
target/arm/cpu-features.h | 16 ++++++++--------
target/arm/cpu.c | 13 +++++--------
target/arm/cpu.h | 2 --
target/arm/cpu64.c | 4 ++--
target/arm/helper.c | 4 ++--
target/arm/kvm.c | 6 ++----
target/arm/tcg/cpu-v7m.c | 12 ++++++------
target/arm/tcg/cpu32.c | 30 ++++++++++++++----------------
target/arm/tcg/cpu64.c | 16 ++++++++--------
10 files changed, 48 insertions(+), 57 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index ac2c4fe4db5c..5cf8cd9321d7 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1274,7 +1274,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset,
MemTxAttrs attrs)
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_dfr0;
+ return GET_IDREG(idregs, ID_DFR0);
case 0xd4c: /* AFR0. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index c49fe8547cc9..e056498fc065 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -299,22 +299,22 @@ static inline bool isar_feature_aa32_ats1e1(const
ARMISARegisters *id)
static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id)
{
/* 0xf means "non-standard IMPDEF PMU" */
- return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
- FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
+ return FIELD_EX32_IDREG(&id->idregs, ID_DFR0, PERFMON) >= 4 &&
+ FIELD_EX32_IDREG(&id->idregs, ID_DFR0, PERFMON) != 0xf;
}
static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id)
{
/* 0xf means "non-standard IMPDEF PMU" */
- return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 &&
- FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
+ return FIELD_EX32_IDREG(&id->idregs, ID_DFR0, PERFMON) >= 5 &&
+ FIELD_EX32_IDREG(&id->idregs, ID_DFR0, PERFMON) != 0xf;
}
static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id)
{
/* 0xf means "non-standard IMPDEF PMU" */
- return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 6 &&
- FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
+ return FIELD_EX32_IDREG(&id->idregs, ID_DFR0, PERFMON) >= 6 &&
+ FIELD_EX32_IDREG(&id->idregs, ID_DFR0, PERFMON) != 0xf;
}
static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
@@ -359,12 +359,12 @@ static inline bool isar_feature_aa32_ssbs(const
ARMISARegisters *id)
static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 5;
+ return FIELD_EX32_IDREG(&id->idregs, ID_DFR0, COPDBG) >= 5;
}
static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8;
+ return FIELD_EX32_IDREG(&id->idregs, ID_DFR0, COPDBG) >= 8;
}
static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 8d0a5d7c46da..fee822eaf416 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2328,7 +2328,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
* feature registers as well.
*/
FIELD_DP32_IDREG(idregs, ID_PFR1, SECURITY, 0);
- cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
+ FIELD_DP32_IDREG(idregs, ID_DFR0, COPSDBG, 0);
FIELD_DP64_IDREG(idregs, ID_AA64PFR0, EL3, 0);
/* Disable the realm management extension, which requires EL3. */
@@ -2356,7 +2356,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
#endif
} else {
FIELD_DP64_IDREG(idregs, ID_AA64DFR0, PMUVER, 0);
- cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0);
+ FIELD_DP32_IDREG(idregs, ID_DFR0, PERFMON, 0);
cpu->pmceid0 = 0;
cpu->pmceid1 = 0;
}
@@ -2419,15 +2419,12 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
FIELD_DP64_IDREG(idregs, ID_AA64DFR0, TRACEBUFFER, 0);
/* FEAT_TRF (Self-hosted Trace Extension) */
FIELD_DP64_IDREG(idregs, ID_AA64DFR0, TRACEFILT, 0);
- cpu->isar.id_dfr0 =
- FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0);
+ FIELD_DP32_IDREG(idregs, ID_DFR0, TRACEFILT, 0);
/* Trace Macrocell system register access */
FIELD_DP64_IDREG(idregs, ID_AA64DFR0, TRACEVER, 0);
- cpu->isar.id_dfr0 =
- FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0);
+ FIELD_DP32_IDREG(idregs, ID_DFR0, COPTRC, 0);
/* Memory mapped trace */
- cpu->isar.id_dfr0 =
- FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0);
+ FIELD_DP32_IDREG(idregs, ID_DFR0, MMAPTRC, 0);
/* FEAT_AMU (Activity Monitors Extension) */
FIELD_DP64_IDREG(idregs, ID_AA64PFR0, AMU, 0);
FIELD_DP32_IDREG(idregs, ID_PFR0, AMU, 0);
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 38b85035c366..df1506ab74fe 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1089,8 +1089,6 @@ struct ArchCPU {
uint32_t mvfr0;
uint32_t mvfr1;
uint32_t mvfr2;
- uint32_t id_dfr0;
- uint32_t id_dfr1;
uint32_t dbgdidr;
uint32_t dbgdevid;
uint32_t dbgdevid1;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index a25b30157965..fb3845c8cceb 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -614,7 +614,7 @@ static void aarch64_a57_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50838;
SET_IDREG(idregs, ID_PFR0, 0x00000131);
SET_IDREG(idregs, ID_PFR1, 0x00011011);
- cpu->isar.id_dfr0 = 0x03010066;
+ SET_IDREG(idregs, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105;
cpu->isar.id_mmfr1 = 0x40000000;
@@ -676,7 +676,7 @@ static void aarch64_a53_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50838;
SET_IDREG(idregs, ID_PFR0, 0x00000131);
SET_IDREG(idregs, ID_PFR1, 0x00011011);
- cpu->isar.id_dfr0 = 0x03010066;
+ SET_IDREG(idregs, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105;
cpu->isar.id_mmfr1 = 0x40000000;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ade5355c71ee..90db2baff200 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8766,7 +8766,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_dfr0 },
+ .resetvalue = GET_IDREG(idregs, ID_DFR0)},
{ .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST,
@@ -9105,7 +9105,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_dfr1 },
+ .resetvalue = GET_IDREG(idregs, ID_DFR1)},
{ .name = "ID_MMFR5", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 287f5ee849a4..88fa08e390d5 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -377,8 +377,7 @@ static bool
kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
*/
err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR0_EL1);
err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR1_EL1);
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
- ARM64_SYS_REG(3, 0, 0, 1, 2));
+ err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_DFR0_EL1);
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
ARM64_SYS_REG(3, 0, 0, 1, 4));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1,
@@ -404,8 +403,7 @@ static bool
kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2,
ARM64_SYS_REG(3, 0, 0, 3, 2));
err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_PFR2_EL1);
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1,
- ARM64_SYS_REG(3, 0, 0, 3, 5));
+ err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_DFR1_EL1);
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5,
ARM64_SYS_REG(3, 0, 0, 3, 6));
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
index e9a02bada8d1..a7034ce5b66c 100644
--- a/target/arm/tcg/cpu-v7m.c
+++ b/target/arm/tcg/cpu-v7m.c
@@ -62,7 +62,7 @@ static void cortex_m0_initfn(Object *obj)
*/
SET_IDREG(idregs, ID_PFR0, 0x00000030);
SET_IDREG(idregs, ID_PFR1, 0x00000200);
- cpu->isar.id_dfr0 = 0x00100000;
+ SET_IDREG(idregs, ID_DFR0, 0x00100000);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00000030;
cpu->isar.id_mmfr1 = 0x00000000;
@@ -88,7 +88,7 @@ static void cortex_m3_initfn(Object *obj)
cpu->pmsav7_dregion = 8;
SET_IDREG(idregs, ID_PFR0, 0x00000030);
SET_IDREG(idregs, ID_PFR1, 0x00000200);
- cpu->isar.id_dfr0 = 0x00100000;
+ SET_IDREG(idregs, ID_DFR0, 0x00100000);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00000030;
cpu->isar.id_mmfr1 = 0x00000000;
@@ -119,7 +119,7 @@ static void cortex_m4_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000000;
SET_IDREG(idregs, ID_PFR0, 0x00000030);
SET_IDREG(idregs, ID_PFR1, 0x00000200);
- cpu->isar.id_dfr0 = 0x00100000;
+ SET_IDREG(idregs, ID_DFR0, 0x00100000);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00000030;
cpu->isar.id_mmfr1 = 0x00000000;
@@ -150,7 +150,7 @@ static void cortex_m7_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000040;
SET_IDREG(idregs, ID_PFR0, 0x00000030);
SET_IDREG(idregs, ID_PFR1, 0x00000200);
- cpu->isar.id_dfr0 = 0x00100000;
+ SET_IDREG(idregs, ID_DFR0, 0x00100000);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00100030;
cpu->isar.id_mmfr1 = 0x00000000;
@@ -183,7 +183,7 @@ static void cortex_m33_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000040;
SET_IDREG(idregs, ID_PFR0, 0x00000030);
SET_IDREG(idregs, ID_PFR1, 0x00000210);
- cpu->isar.id_dfr0 = 0x00200000;
+ SET_IDREG(idregs, ID_DFR0, 0x00200000);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00101F40;
cpu->isar.id_mmfr1 = 0x00000000;
@@ -221,7 +221,7 @@ static void cortex_m55_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000040;
SET_IDREG(idregs, ID_PFR0, 0x20000030);
SET_IDREG(idregs, ID_PFR1, 0x00000230);
- cpu->isar.id_dfr0 = 0x10200000;
+ SET_IDREG(idregs, ID_DFR0, 0x10200000);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00111040;
cpu->isar.id_mmfr1 = 0x00000000;
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 9ac76c61109d..3036c39d00f1 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -82,11 +82,11 @@ void aa32_max_features(ARMCPU *cpu)
t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
SET_IDREG(idregs, ID_PFR2, t);
- t = cpu->isar.id_dfr0;
+ t = GET_IDREG(idregs, ID_DFR0);
t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */
t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */
t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
- cpu->isar.id_dfr0 = t;
+ SET_IDREG(idregs, ID_DFR0, t);
/* Debug ID registers. */
@@ -116,9 +116,7 @@ void aa32_max_features(ARMCPU *cpu)
t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2);
cpu->isar.dbgdevid1 = t;
- t = cpu->isar.id_dfr1;
- t = FIELD_DP32(t, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */
- cpu->isar.id_dfr1 = t;
+ FIELD_DP32_IDREG(idregs, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */
}
/* CPU models. These are not needed for the AArch64 linux-user build. */
@@ -230,7 +228,7 @@ static void arm1136_r2_initfn(Object *obj)
cpu->reset_sctlr = 0x00050078;
SET_IDREG(idregs, ID_PFR0, 0x111);
SET_IDREG(idregs, ID_PFR1, 0x1);
- cpu->isar.id_dfr0 = 0x2;
+ SET_IDREG(idregs, ID_DFR0, 0x2);
cpu->id_afr0 = 0x3;
cpu->isar.id_mmfr0 = 0x01130003;
cpu->isar.id_mmfr1 = 0x10030302;
@@ -262,7 +260,7 @@ static void arm1136_initfn(Object *obj)
cpu->reset_sctlr = 0x00050078;
SET_IDREG(idregs, ID_PFR0, 0x111);
SET_IDREG(idregs, ID_PFR1, 0x1);
- cpu->isar.id_dfr0 = 0x2;
+ SET_IDREG(idregs, ID_DFR0, 0x2);
cpu->id_afr0 = 0x3;
cpu->isar.id_mmfr0 = 0x01130003;
cpu->isar.id_mmfr1 = 0x10030302;
@@ -295,7 +293,7 @@ static void arm1176_initfn(Object *obj)
cpu->reset_sctlr = 0x00050078;
SET_IDREG(idregs, ID_PFR0, 0x111);
SET_IDREG(idregs, ID_PFR1, 0x11);
- cpu->isar.id_dfr0 = 0x33;
+ SET_IDREG(idregs, ID_DFR0, 0x33);
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x01130003;
cpu->isar.id_mmfr1 = 0x10030302;
@@ -325,7 +323,7 @@ static void arm11mpcore_initfn(Object *obj)
cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
SET_IDREG(idregs, ID_PFR0, 0x111);
SET_IDREG(idregs, ID_PFR1, 0x1);
- cpu->isar.id_dfr0 = 0;
+ SET_IDREG(idregs, ID_DFR0, 0);
cpu->id_afr0 = 0x2;
cpu->isar.id_mmfr0 = 0x01100103;
cpu->isar.id_mmfr1 = 0x10020302;
@@ -365,7 +363,7 @@ static void cortex_a8_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50078;
SET_IDREG(idregs, ID_PFR0, 0x1031);
SET_IDREG(idregs, ID_PFR1, 0x11);
- cpu->isar.id_dfr0 = 0x400;
+ SET_IDREG(idregs, ID_DFR0, 0x400);
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x31100003;
cpu->isar.id_mmfr1 = 0x20000000;
@@ -441,7 +439,7 @@ static void cortex_a9_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50078;
SET_IDREG(idregs, ID_PFR0, 0x1031);
SET_IDREG(idregs, ID_PFR1, 0x11);
- cpu->isar.id_dfr0 = 0x000;
+ SET_IDREG(idregs, ID_DFR0, 0x000);
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x00100103;
cpu->isar.id_mmfr1 = 0x20000000;
@@ -507,7 +505,7 @@ static void cortex_a7_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50078;
SET_IDREG(idregs, ID_PFR0, 0x00001131);
SET_IDREG(idregs, ID_PFR1, 0x00011011);
- cpu->isar.id_dfr0 = 0x02010555;
+ SET_IDREG(idregs, ID_DFR0, 0x02010555);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105;
cpu->isar.id_mmfr1 = 0x40000000;
@@ -559,7 +557,7 @@ static void cortex_a15_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50078;
SET_IDREG(idregs, ID_PFR0, 0x00001131);
SET_IDREG(idregs, ID_PFR1, 0x00011011);
- cpu->isar.id_dfr0 = 0x02010555;
+ SET_IDREG(idregs, ID_DFR0, 0x02010555);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x20000000;
@@ -603,7 +601,7 @@ static void cortex_r5_initfn(Object *obj)
cpu->midr = 0x411fc153; /* r1p3 */
SET_IDREG(idregs, ID_PFR0, 0x0131);
SET_IDREG(idregs, ID_PFR1, 0x001);
- cpu->isar.id_dfr0 = 0x010400;
+ SET_IDREG(idregs, ID_DFR0, 0x010400);
cpu->id_afr0 = 0x0;
cpu->isar.id_mmfr0 = 0x0210030;
cpu->isar.id_mmfr1 = 0x00000000;
@@ -750,7 +748,7 @@ static void cortex_r52_initfn(Object *obj)
cpu->reset_sctlr = 0x30c50838;
SET_IDREG(idregs, ID_PFR0, 0x00000131);
SET_IDREG(idregs, ID_PFR1, 0x10111001);
- cpu->isar.id_dfr0 = 0x03010006;
+ SET_IDREG(idregs, ID_DFR0, 0x03010006);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00211040;
cpu->isar.id_mmfr1 = 0x40000000;
@@ -982,7 +980,7 @@ static void arm_max_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50838;
SET_IDREG(idregs, ID_PFR0, 0x00000131);
SET_IDREG(idregs, ID_PFR1, 0x00011011);
- cpu->isar.id_dfr0 = 0x03010066;
+ SET_IDREG(idregs, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105;
cpu->isar.id_mmfr1 = 0x40000000;
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 42662878b2df..ead0b5600024 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -51,7 +51,7 @@ static void aarch64_a35_initfn(Object *obj)
cpu->ctr = 0x84448004;
SET_IDREG(idregs, ID_PFR0, 0x00000131);
SET_IDREG(idregs, ID_PFR1, 0x00011011);
- cpu->isar.id_dfr0 = 0x03010066;
+ SET_IDREG(idregs, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x40000000;
@@ -228,7 +228,7 @@ static void aarch64_a55_initfn(Object *obj)
SET_IDREG(idregs, ID_AA64PFR0, 0x0000000010112222ull);
SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000010ull);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x04010088;
+ SET_IDREG(idregs, ID_DFR0, 0x04010088);
SET_IDREG(idregs, ID_ISAR0, 0x02101110);
SET_IDREG(idregs, ID_ISAR1, 0x13112111);
SET_IDREG(idregs, ID_ISAR2, 0x21232042);
@@ -297,7 +297,7 @@ static void aarch64_a72_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50838;
SET_IDREG(idregs, ID_PFR0, 0x00000131);
SET_IDREG(idregs, ID_PFR1, 0x00011011);
- cpu->isar.id_dfr0 = 0x03010066;
+ SET_IDREG(idregs, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x40000000;
@@ -361,7 +361,7 @@ static void aarch64_a76_initfn(Object *obj)
SET_IDREG(idregs, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in
later */
SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000010ull);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x04010088;
+ SET_IDREG(idregs, ID_DFR0, 0x04010088);
SET_IDREG(idregs, ID_ISAR0, 0x02101110);
SET_IDREG(idregs, ID_ISAR1, 0x13112111);
SET_IDREG(idregs, ID_ISAR2, 0x21232042);
@@ -609,7 +609,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
SET_IDREG(idregs, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in
later */
SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000020ull);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x04010088;
+ SET_IDREG(idregs, ID_DFR0, 0x04010088);
SET_IDREG(idregs, ID_ISAR0, 0x02101110);
SET_IDREG(idregs, ID_ISAR1, 0x13112111);
SET_IDREG(idregs, ID_ISAR2, 0x21232042);
@@ -688,7 +688,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
SET_IDREG(idregs, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled in
later */
SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000020ull);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x15011099;
+ SET_IDREG(idregs, ID_DFR0, 0x15011099);
SET_IDREG(idregs, ID_ISAR0, 0x02101110);
SET_IDREG(idregs, ID_ISAR1, 0x13112111);
SET_IDREG(idregs, ID_ISAR2, 0x21232042);
@@ -904,7 +904,7 @@ static void aarch64_a710_initfn(Object *obj)
cpu->revidr = 0;
SET_IDREG(idregs, ID_PFR0, 0x21110131);
SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */
- cpu->isar.id_dfr0 = 0x16011099;
+ SET_IDREG(idregs, ID_DFR0, 0x16011099);
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x40000000;
@@ -1007,7 +1007,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
cpu->revidr = 0;
SET_IDREG(idregs, ID_PFR0, 0x21110131);
SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */
- cpu->isar.id_dfr0 = 0x16011099;
+ SET_IDREG(idregs, ID_DFR0, 0x16011099);
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x40000000;
--
2.47.0
- Re: [PATCH RFCv2 02/20] arm/cpu: Add sysreg definitions in cpu-sysregs.h, (continued)
[PATCH RFCv2 03/20] arm/cpu: Store aa64isar0 into the idregs arrays, Cornelia Huck, 2024/12/06
[PATCH RFCv2 04/20] arm/cpu: Store aa64isar1/2 into the idregs array, Cornelia Huck, 2024/12/06
[PATCH RFCv2 07/20] arm/cpu: Store aa64drf0/1 into the idregs array, Cornelia Huck, 2024/12/06
[PATCH RFCv2 05/20] arm/cpu: Store aa64drf0/1 into the idregs array, Cornelia Huck, 2024/12/06
[PATCH RFCv2 06/20] arm/cpu: Store aa64mmfr0-3 into the idregs array, Cornelia Huck, 2024/12/06
[PATCH RFCv2 08/20] arm/cpu: Store aa64smfr0 into the idregs array, Cornelia Huck, 2024/12/06
[PATCH RFCv2 09/20] arm/cpu: Store id_isar0-7 into the idregs array, Cornelia Huck, 2024/12/06
[PATCH RFCv2 10/20] arm/cpu: Store id_mfr0/1 into the idregs array, Cornelia Huck, 2024/12/06
[PATCH RFCv2 11/20] arm/cpu: Store id_dfr0/1 into the idregs array,
Cornelia Huck <=
[PATCH RFCv2 13/20] arm/cpu: Add infra to handle generated ID register definitions, Cornelia Huck, 2024/12/06
[PATCH RFCv2 12/20] arm/cpu: Store id_mmfr0-5 into the idregs array, Cornelia Huck, 2024/12/06
[PATCH RFCv2 15/20] arm/cpu: Add generated files, Cornelia Huck, 2024/12/06
[PATCH RFCv2 16/20] arm/kvm: Allow reading all the writable ID registers, Cornelia Huck, 2024/12/06
[PATCH RFCv2 18/20] arm/cpu: more customization for the kvm host cpu model, Cornelia Huck, 2024/12/06
[PATCH RFCv2 17/20] arm/kvm: write back modified ID regs to KVM, Cornelia Huck, 2024/12/06
[PATCH RFCv2 19/20] arm-qmp-cmds: introspection for ID register props, Cornelia Huck, 2024/12/06
[PATCH RFCv2 14/20] arm/cpu: Add sysreg generation scripts, Cornelia Huck, 2024/12/06
[PATCH RFCv2 20/20] arm/cpu-features: document ID reg properties, Cornelia Huck, 2024/12/06
Re: [PATCH RFCv2 00/20] kvm/arm: Introduce a customizable aarch64 KVM host model, Eric Auger, 2024/12/12