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[PATCH v3 20/69] target/arm: Introduce fp_access_check_scalar_hsd
From: |
Richard Henderson |
Subject: |
[PATCH v3 20/69] target/arm: Introduce fp_access_check_scalar_hsd |
Date: |
Wed, 11 Dec 2024 10:29:47 -0600 |
Provide a simple way to check for float64, float32,
and float16 support, as well as the fpu enabled.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 62 ++++++++++++++++++----------------
1 file changed, 32 insertions(+), 30 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 9c6365f5ef..4e47b8a804 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -1239,6 +1239,27 @@ static bool fp_access_check(DisasContext *s)
return true;
}
+/*
+ * Return <0 for non-supported element sizes, with MO_16 controlled by
+ * FEAT_FP16; return 0 for fp disabled; otherwise return >0 for success.
+ */
+static int fp_access_check_scalar_hsd(DisasContext *s, MemOp esz)
+{
+ switch (esz) {
+ case MO_64:
+ case MO_32:
+ break;
+ case MO_16:
+ if (!dc_isar_feature(aa64_fp16, s)) {
+ return -1;
+ }
+ break;
+ default:
+ return -1;
+ }
+ return fp_access_check(s);
+}
+
/*
* Check that SVE access is enabled. If it is, return true.
* If not, emit code to generate an appropriate exception and return false.
@@ -6628,22 +6649,10 @@ static bool trans_FCSEL(DisasContext *s, arg_FCSEL *a)
{
TCGv_i64 t_true, t_false;
DisasCompare64 c;
+ int check = fp_access_check_scalar_hsd(s, a->esz);
- switch (a->esz) {
- case MO_32:
- case MO_64:
- break;
- case MO_16:
- if (!dc_isar_feature(aa64_fp16, s)) {
- return false;
- }
- break;
- default:
- return false;
- }
-
- if (!fp_access_check(s)) {
- return true;
+ if (check <= 0) {
+ return check == 0;
}
/* Zero extend sreg & hreg inputs to 64 bits now. */
@@ -6894,22 +6903,15 @@ TRANS(FMINV_s, do_fp_reduction, a, gen_helper_vfp_mins)
static bool trans_FMOVI_s(DisasContext *s, arg_FMOVI_s *a)
{
- switch (a->esz) {
- case MO_32:
- case MO_64:
- break;
- case MO_16:
- if (!dc_isar_feature(aa64_fp16, s)) {
- return false;
- }
- break;
- default:
- return false;
- }
- if (fp_access_check(s)) {
- uint64_t imm = vfp_expand_imm(a->esz, a->imm);
- write_fp_dreg(s, a->rd, tcg_constant_i64(imm));
+ int check = fp_access_check_scalar_hsd(s, a->esz);
+ uint64_t imm;
+
+ if (check <= 0) {
+ return check == 0;
}
+
+ imm = vfp_expand_imm(a->esz, a->imm);
+ write_fp_dreg(s, a->rd, tcg_constant_i64(imm));
return true;
}
--
2.43.0
- [PATCH v3 05/69] target/arm: Convert SUBP, IRG, GMI to decodetree, (continued)
- [PATCH v3 05/69] target/arm: Convert SUBP, IRG, GMI to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 09/69] target/arm: Convert PAC[ID]*, AUT[ID]* to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 14/69] target/arm: Convert disas_data_proc_3src to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 13/69] target/arm: Convert disas_add_sub_reg to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 18/69] target/arm: Convert CCMP, CCMN to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 11/69] target/arm: Convert disas_logic_reg to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 12/69] target/arm: Convert disas_add_sub_ext_reg to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 15/69] target/arm: Convert disas_adc_sbc to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 16/69] target/arm: Convert RMIF to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 19/69] target/arm: Convert disas_cond_select to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 20/69] target/arm: Introduce fp_access_check_scalar_hsd,
Richard Henderson <=
- [PATCH v3 24/69] target/arm: Convert FMOV, FABS, FNEG (scalar) to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 17/69] target/arm: Convert SETF8, SETF16 to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 22/69] target/arm: Convert FCMP, FCMPE, FCCMP, FCCMPE to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 30/69] target/arm: Convert FRINT{32, 64}[ZX] (scalar) to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 33/69] target/arm: Convert FJCVTZS to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 38/69] target/arm: Convert CLS, CLZ (vector) to decodetree, Richard Henderson, 2024/12/11
- [PATCH v3 39/69] target/arm: Introduce gen_gvec_cnt, gen_gvec_rbit, Richard Henderson, 2024/12/11
- [PATCH v3 21/69] target/arm: Introduce fp_access_check_vector_hsd, Richard Henderson, 2024/12/11
- [PATCH v3 26/69] target/arm: Remove helper_sqrt_f16, Richard Henderson, 2024/12/11
- [PATCH v3 25/69] target/arm: Pass fpstatus to vfp_sqrt*, Richard Henderson, 2024/12/11