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[PULL 3/5] target/hexagon: add enums for event, cause
From: |
Brian Cain |
Subject: |
[PULL 3/5] target/hexagon: add enums for event, cause |
Date: |
Thu, 12 Dec 2024 20:18:34 -0800 |
From: Brian Cain <bcain@quicinc.com>
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
target/hexagon/cpu_bits.h | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
index 2e60c0fafe..ff596e2a94 100644
--- a/target/hexagon/cpu_bits.h
+++ b/target/hexagon/cpu_bits.h
@@ -23,15 +23,21 @@
#define PCALIGN 4
#define PCALIGN_MASK (PCALIGN - 1)
-#define HEX_EVENT_TRAP0 0x008
+enum hex_event {
+ HEX_EVENT_NONE = -1,
+ HEX_EVENT_TRAP0 = 0x008,
+};
-#define HEX_CAUSE_TRAP0 0x172
-#define HEX_CAUSE_FETCH_NO_UPAGE 0x012
-#define HEX_CAUSE_INVALID_PACKET 0x015
-#define HEX_CAUSE_INVALID_OPCODE 0x015
-#define HEX_CAUSE_PC_NOT_ALIGNED 0x01e
-#define HEX_CAUSE_PRIV_NO_UREAD 0x024
-#define HEX_CAUSE_PRIV_NO_UWRITE 0x025
+enum hex_cause {
+ HEX_CAUSE_NONE = -1,
+ HEX_CAUSE_TRAP0 = 0x172,
+ HEX_CAUSE_FETCH_NO_UPAGE = 0x012,
+ HEX_CAUSE_INVALID_PACKET = 0x015,
+ HEX_CAUSE_INVALID_OPCODE = 0x015,
+ HEX_CAUSE_PC_NOT_ALIGNED = 0x01e,
+ HEX_CAUSE_PRIV_NO_UREAD = 0x024,
+ HEX_CAUSE_PRIV_NO_UWRITE = 0x025,
+};
#define PACKET_WORDS_MAX 4
--
2.34.1
- [PULL 0/5] hex queue, Brian Cain, 2024/12/12
- [PULL 3/5] target/hexagon: add enums for event, cause,
Brian Cain <=
- [PULL 1/5] Hexagon (target/hexagon) Remove HEX_DEBUG/HEX_DEBUG_LOG, Brian Cain, 2024/12/12
- [PULL 5/5] target/hexagon: Make HVX vector args. restrict *, Brian Cain, 2024/12/12
- [PULL 2/5] target/hexagon: rename HEX_EXCP_*=>HEX_CAUSE_*, Brian Cain, 2024/12/12
- [PULL 4/5] target/hexagon: Use argparse in all python scripts, Brian Cain, 2024/12/12
- Re: [PULL 0/5] hex queue, Brian Cain, 2024/12/14
- Re: [PULL 0/5] hex queue, Stefan Hajnoczi, 2024/12/16