[PULL 00/85] target-arm queue

[Peter Maydell]

Another very large pullreq (this one mostly because it has
RTH's decodetree conversion series in it), but this should be
the last of the really large things in my to-review queue...

thanks
-- PMM

The following changes since commit 83aaec1d5a49f158abaa31797a0f976b3c07e5ca:

  Merge tag 'pull-tcg-20241212' of https://gitlab.com/rth7680/qemu into staging 
(2024-12-12 18:45:39 -0500)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20241213

for you to fetch changes up to 48e652c4bd9570f6f24def25355cb3009a7300f8:

  target/arm: Simplify condition for tlbi_el2_cp_reginfo[] (2024-12-13 15:41:09 
+0000)

----------------------------------------------------------------
target-arm queue:
 * Finish conversion of A64 decoder to decodetree
 * Use float_round_to_odd in helper_fcvtx_f64_to_f32
 * Move TLBI insn emulation code out to its own source file
 * docs/system/arm: fix broken links, document undocumented properties
 * MAINTAINERS: correct an email address

----------------------------------------------------------------
Brian Cain (1):
      MAINTAINERS: correct my email address

Peter Maydell (10):
      target/arm: Move some TLBI insns to their own source file
      target/arm: Move TLBI insns for AArch32 EL2 to tlbi_insn_helper.c
      target/arm: Move AArch64 TLBI insns from v8_cp_reginfo[]
      target/arm: Move the AArch64 EL2 TLBI insns
      target/arm: Move AArch64 EL3 TLBI insns
      target/arm: Move TLBI range insns
      target/arm: Move the TLBI OS insns to tlb-insns.c.
      target/arm: Move small helper functions to tlb-insns.c
      target/arm: Move RME TLB insns to tlb-insns.c
      target/arm: Simplify condition for tlbi_el2_cp_reginfo[]

Pierrick Bouvier (4):
      docs/system/arm/orangepi: update links
      docs/system/arm/fby35: document execute-in-place property
      docs/system/arm/xlnx-versal-virt: document ospi-flash property
      docs/system/arm/virt: document missing properties

Richard Henderson (70):
      target/arm: Add section labels for "Data Processing (register)"
      target/arm: Convert UDIV, SDIV to decodetree
      target/arm: Convert LSLV, LSRV, ASRV, RORV to decodetree
      target/arm: Convert CRC32, CRC32C to decodetree
      target/arm: Convert SUBP, IRG, GMI to decodetree
      target/arm: Convert PACGA to decodetree
      target/arm: Convert RBIT, REV16, REV32, REV64 to decodetree
      target/arm: Convert CLZ, CLS to decodetree
      target/arm: Convert PAC[ID]*, AUT[ID]* to decodetree
      target/arm: Convert XPAC[ID] to decodetree
      target/arm: Convert disas_logic_reg to decodetree
      target/arm: Convert disas_add_sub_ext_reg to decodetree
      target/arm: Convert disas_add_sub_reg to decodetree
      target/arm: Convert disas_data_proc_3src to decodetree
      target/arm: Convert disas_adc_sbc to decodetree
      target/arm: Convert RMIF to decodetree
      target/arm: Convert SETF8, SETF16 to decodetree
      target/arm: Convert CCMP, CCMN to decodetree
      target/arm: Convert disas_cond_select to decodetree
      target/arm: Introduce fp_access_check_scalar_hsd
      target/arm: Introduce fp_access_check_vector_hsd
      target/arm: Convert FCMP, FCMPE, FCCMP, FCCMPE to decodetree
      target/arm: Fix decode of fp16 vector fabs, fneg, fsqrt
      target/arm: Convert FMOV, FABS, FNEG (scalar) to decodetree
      target/arm: Pass fpstatus to vfp_sqrt*
      target/arm: Remove helper_sqrt_f16
      target/arm: Convert FSQRT (scalar) to decodetree
      target/arm: Convert FRINT[NPMSAXI] (scalar) to decodetree
      target/arm: Convert BFCVT to decodetree
      target/arm: Convert FRINT{32, 64}[ZX] (scalar) to decodetree
      target/arm: Convert FCVT (scalar) to decodetree
      target/arm: Convert handle_fpfpcvt to decodetree
      target/arm: Convert FJCVTZS to decodetree
      target/arm: Convert handle_fmov to decodetree
      target/arm: Convert SQABS, SQNEG to decodetree
      target/arm: Convert ABS, NEG to decodetree
      target/arm: Introduce gen_gvec_cls, gen_gvec_clz
      target/arm: Convert CLS, CLZ (vector) to decodetree
      target/arm: Introduce gen_gvec_cnt, gen_gvec_rbit
      target/arm: Convert CNT, NOT, RBIT (vector) to decodetree
      target/arm: Convert CMGT, CMGE, GMLT, GMLE, CMEQ (zero) to decodetree
      target/arm: Introduce gen_gvec_rev{16,32,64}
      target/arm: Convert handle_rev to decodetree
      target/arm: Move helper_neon_addlp_{s8, s16} to neon_helper.c
      target/arm: Introduce gen_gvec_{s,u}{add,ada}lp
      target/arm: Convert handle_2misc_pairwise to decodetree
      target/arm: Remove helper_neon_{add,sub}l_u{16,32}
      target/arm: Introduce clear_vec
      target/arm: Convert XTN, SQXTUN, SQXTN, UQXTN to decodetree
      target/arm: Convert FCVTN, BFCVTN to decodetree
      target/arm: Convert FCVTXN to decodetree
      target/arm: Convert SHLL to decodetree
      target/arm: Implement gen_gvec_fabs, gen_gvec_fneg
      target/arm: Convert FABS, FNEG (vector) to decodetree
      target/arm: Convert FSQRT (vector) to decodetree
      target/arm: Convert FRINT* (vector) to decodetree
      target/arm: Convert FCVT* (vector, integer) scalar to decodetree
      target/arm: Convert FCVT* (vector, fixed-point) scalar to decodetree
      target/arm: Convert [US]CVTF (vector, integer) scalar to decodetree
      target/arm: Convert [US]CVTF (vector, fixed-point) scalar to decodetree
      target/arm: Rename helper_gvec_vcvt_[hf][su] with _rz
      target/arm: Convert [US]CVTF (vector) to decodetree
      target/arm: Convert FCVTZ[SU] (vector, fixed-point) to decodetree
      target/arm: Convert FCVT* (vector, integer) to decodetree
      target/arm: Convert handle_2misc_fcmp_zero to decodetree
      target/arm: Convert FRECPE, FRECPX, FRSQRTE to decodetree
      target/arm: Introduce gen_gvec_urecpe, gen_gvec_ursqrte
      target/arm: Convert URECPE and URSQRTE to decodetree
      target/arm: Convert FCVTL to decodetree
      target/arm: Use float_round_to_odd in helper_fcvtx_f64_to_f32

 MAINTAINERS                          |    2 +-
 docs/system/arm/fby35.rst            |    5 +
 docs/system/arm/orangepi.rst         |    4 +-
 docs/system/arm/virt.rst             |   16 +
 docs/system/arm/xlnx-versal-virt.rst |    3 +
 target/arm/helper.h                  |   43 +-
 target/arm/internals.h               |    9 +
 target/arm/tcg/helper-a64.h          |    7 -
 target/arm/tcg/translate.h           |   35 +
 target/arm/tcg/a64.decode            |  502 ++-
 target/arm/helper.c                  | 1208 +-------
 target/arm/tcg-stubs.c               |    5 +
 target/arm/tcg/gengvec.c             |  369 +++
 target/arm/tcg/helper-a64.c          |  122 +-
 target/arm/tcg/neon_helper.c         |  106 +-
 target/arm/tcg/tlb-insns.c           | 1266 ++++++++
 target/arm/tcg/translate-a64.c       | 5670 +++++++++++-----------------------
 target/arm/tcg/translate-neon.c      |  337 +-
 target/arm/tcg/translate-vfp.c       |    6 +-
 target/arm/tcg/vec_helper.c          |   65 +-
 target/arm/vfp_helper.c              |   16 +-
 target/arm/tcg/meson.build           |    1 +
 22 files changed, 4203 insertions(+), 5594 deletions(-)
 create mode 100644 target/arm/tcg/tlb-insns.c