[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 70/85] target/arm: Use float_round_to_odd in helper_fcvtx_f64_to_f
From: |
Peter Maydell |
Subject: |
[PULL 70/85] target/arm: Use float_round_to_odd in helper_fcvtx_f64_to_f32 |
Date: |
Fri, 13 Dec 2024 17:32:14 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
Softfloat has native support for round-to-odd. Use it.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241206031428.78634-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/helper-a64.c | 18 ++++--------------
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index 28de7468cd1..fb6fe0fcaa9 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -408,23 +408,13 @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env)
{
- /* Von Neumann rounding is implemented by using round-to-zero
- * and then setting the LSB of the result if Inexact was raised.
- */
float32 r;
float_status *fpst = &env->vfp.fp_status;
- float_status tstat = *fpst;
- int exflags;
+ int old = get_float_rounding_mode(fpst);
- set_float_rounding_mode(float_round_to_zero, &tstat);
- set_float_exception_flags(0, &tstat);
- r = float64_to_float32(a, &tstat);
- exflags = get_float_exception_flags(&tstat);
- if (exflags & float_flag_inexact) {
- r = make_float32(float32_val(r) | 1);
- }
- exflags |= get_float_exception_flags(fpst);
- set_float_exception_flags(exflags, fpst);
+ set_float_rounding_mode(float_round_to_odd, fpst);
+ r = float64_to_float32(a, fpst);
+ set_float_rounding_mode(old, fpst);
return r;
}
--
2.34.1
- [PULL 48/85] target/arm: Introduce clear_vec, (continued)
- [PULL 48/85] target/arm: Introduce clear_vec, Peter Maydell, 2024/12/13
- [PULL 51/85] target/arm: Convert FCVTXN to decodetree, Peter Maydell, 2024/12/13
- [PULL 57/85] target/arm: Convert FCVT* (vector, integer) scalar to decodetree, Peter Maydell, 2024/12/13
- [PULL 55/85] target/arm: Convert FSQRT (vector) to decodetree, Peter Maydell, 2024/12/13
- [PULL 11/85] target/arm: Convert disas_logic_reg to decodetree, Peter Maydell, 2024/12/13
- [PULL 68/85] target/arm: Convert URECPE and URSQRTE to decodetree, Peter Maydell, 2024/12/13
- [PULL 59/85] target/arm: Convert [US]CVTF (vector, integer) scalar to decodetree, Peter Maydell, 2024/12/13
- [PULL 62/85] target/arm: Convert [US]CVTF (vector) to decodetree, Peter Maydell, 2024/12/13
- [PULL 66/85] target/arm: Convert FRECPE, FRECPX, FRSQRTE to decodetree, Peter Maydell, 2024/12/13
- [PULL 75/85] MAINTAINERS: correct my email address, Peter Maydell, 2024/12/13
- [PULL 70/85] target/arm: Use float_round_to_odd in helper_fcvtx_f64_to_f32,
Peter Maydell <=
- [PULL 80/85] target/arm: Move AArch64 EL3 TLBI insns, Peter Maydell, 2024/12/13
- [PULL 81/85] target/arm: Move TLBI range insns, Peter Maydell, 2024/12/13
- [PULL 12/85] target/arm: Convert disas_add_sub_ext_reg to decodetree, Peter Maydell, 2024/12/13
- [PULL 10/85] target/arm: Convert XPAC[ID] to decodetree, Peter Maydell, 2024/12/13
- [PULL 14/85] target/arm: Convert disas_data_proc_3src to decodetree, Peter Maydell, 2024/12/13
- [PULL 18/85] target/arm: Convert CCMP, CCMN to decodetree, Peter Maydell, 2024/12/13
- [PULL 16/85] target/arm: Convert RMIF to decodetree, Peter Maydell, 2024/12/13
- [PULL 19/85] target/arm: Convert disas_cond_select to decodetree, Peter Maydell, 2024/12/13
- [PULL 23/85] target/arm: Fix decode of fp16 vector fabs, fneg, fsqrt, Peter Maydell, 2024/12/13
- [PULL 26/85] target/arm: Remove helper_sqrt_f16, Peter Maydell, 2024/12/13