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[PULL 61/85] target/arm: Rename helper_gvec_vcvt_[hf][su] with _rz
From: |
Peter Maydell |
Subject: |
[PULL 61/85] target/arm: Rename helper_gvec_vcvt_[hf][su] with _rz |
Date: |
Fri, 13 Dec 2024 17:32:05 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
Emphasize that these functions use round-to-zero mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-62-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.h | 8 ++++----
target/arm/tcg/translate-neon.c | 8 ++++----
target/arm/tcg/vec_helper.c | 8 ++++----
3 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 04e422ab081..f2cfee40de3 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -650,13 +650,13 @@ DEF_HELPER_FLAGS_4(gvec_touizs, TCG_CALL_NO_RWG, void,
ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_sf, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_uf, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
-DEF_HELPER_FLAGS_4(gvec_vcvt_fs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
-DEF_HELPER_FLAGS_4(gvec_vcvt_fu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_fu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_sh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_uh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
-DEF_HELPER_FLAGS_4(gvec_vcvt_hs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
-DEF_HELPER_FLAGS_4(gvec_vcvt_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_vcvt_rz_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ss, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_vcvt_rm_us, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c
index b9b3d1c1fbc..f9ca889beca 100644
--- a/target/arm/tcg/translate-neon.c
+++ b/target/arm/tcg/translate-neon.c
@@ -1409,13 +1409,13 @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift
*a,
DO_FP_2SH(VCVT_SF, gen_helper_gvec_vcvt_sf)
DO_FP_2SH(VCVT_UF, gen_helper_gvec_vcvt_uf)
-DO_FP_2SH(VCVT_FS, gen_helper_gvec_vcvt_fs)
-DO_FP_2SH(VCVT_FU, gen_helper_gvec_vcvt_fu)
+DO_FP_2SH(VCVT_FS, gen_helper_gvec_vcvt_rz_fs)
+DO_FP_2SH(VCVT_FU, gen_helper_gvec_vcvt_rz_fu)
DO_FP_2SH(VCVT_SH, gen_helper_gvec_vcvt_sh)
DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
-DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
-DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
+DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_rz_hs)
+DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_rz_hu)
static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
GVecGen2iFn *fn)
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index 91a9130641f..ec6b640fdad 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tcg/vec_helper.c
@@ -2507,12 +2507,12 @@ DO_3OP_PAIR(gvec_uminp_s, MIN, uint32_t, H4)
DO_VCVT_FIXED(gvec_vcvt_sf, helper_vfp_sltos, uint32_t)
DO_VCVT_FIXED(gvec_vcvt_uf, helper_vfp_ultos, uint32_t)
-DO_VCVT_FIXED(gvec_vcvt_fs, helper_vfp_tosls_round_to_zero, uint32_t)
-DO_VCVT_FIXED(gvec_vcvt_fu, helper_vfp_touls_round_to_zero, uint32_t)
+DO_VCVT_FIXED(gvec_vcvt_rz_fs, helper_vfp_tosls_round_to_zero, uint32_t)
+DO_VCVT_FIXED(gvec_vcvt_rz_fu, helper_vfp_touls_round_to_zero, uint32_t)
DO_VCVT_FIXED(gvec_vcvt_sh, helper_vfp_shtoh, uint16_t)
DO_VCVT_FIXED(gvec_vcvt_uh, helper_vfp_uhtoh, uint16_t)
-DO_VCVT_FIXED(gvec_vcvt_hs, helper_vfp_toshh_round_to_zero, uint16_t)
-DO_VCVT_FIXED(gvec_vcvt_hu, helper_vfp_touhh_round_to_zero, uint16_t)
+DO_VCVT_FIXED(gvec_vcvt_rz_hs, helper_vfp_toshh_round_to_zero, uint16_t)
+DO_VCVT_FIXED(gvec_vcvt_rz_hu, helper_vfp_touhh_round_to_zero, uint16_t)
#undef DO_VCVT_FIXED
--
2.34.1
- [PULL 52/85] target/arm: Convert SHLL to decodetree, (continued)
- [PULL 52/85] target/arm: Convert SHLL to decodetree, Peter Maydell, 2024/12/13
- [PULL 50/85] target/arm: Convert FCVTN, BFCVTN to decodetree, Peter Maydell, 2024/12/13
- [PULL 54/85] target/arm: Convert FABS, FNEG (vector) to decodetree, Peter Maydell, 2024/12/13
- [PULL 53/85] target/arm: Implement gen_gvec_fabs, gen_gvec_fneg, Peter Maydell, 2024/12/13
- [PULL 07/85] target/arm: Convert RBIT, REV16, REV32, REV64 to decodetree, Peter Maydell, 2024/12/13
- [PULL 39/85] target/arm: Introduce gen_gvec_cnt, gen_gvec_rbit, Peter Maydell, 2024/12/13
- [PULL 45/85] target/arm: Introduce gen_gvec_{s,u}{add,ada}lp, Peter Maydell, 2024/12/13
- [PULL 56/85] target/arm: Convert FRINT* (vector) to decodetree, Peter Maydell, 2024/12/13
- [PULL 60/85] target/arm: Convert [US]CVTF (vector, fixed-point) scalar to decodetree, Peter Maydell, 2024/12/13
- [PULL 58/85] target/arm: Convert FCVT* (vector, fixed-point) scalar to decodetree, Peter Maydell, 2024/12/13
- [PULL 61/85] target/arm: Rename helper_gvec_vcvt_[hf][su] with _rz,
Peter Maydell <=
- [PULL 63/85] target/arm: Convert FCVTZ[SU] (vector, fixed-point) to decodetree, Peter Maydell, 2024/12/13
- [PULL 64/85] target/arm: Convert FCVT* (vector, integer) to decodetree, Peter Maydell, 2024/12/13
- [PULL 67/85] target/arm: Introduce gen_gvec_urecpe, gen_gvec_ursqrte, Peter Maydell, 2024/12/13
- [PULL 72/85] docs/system/arm/fby35: document execute-in-place property, Peter Maydell, 2024/12/13
- [PULL 65/85] target/arm: Convert handle_2misc_fcmp_zero to decodetree, Peter Maydell, 2024/12/13
- [PULL 69/85] target/arm: Convert FCVTL to decodetree, Peter Maydell, 2024/12/13
- [PULL 76/85] target/arm: Move some TLBI insns to their own source file, Peter Maydell, 2024/12/13
- [PULL 79/85] target/arm: Move the AArch64 EL2 TLBI insns, Peter Maydell, 2024/12/13
- [PULL 78/85] target/arm: Move AArch64 TLBI insns from v8_cp_reginfo[], Peter Maydell, 2024/12/13
- [PULL 83/85] target/arm: Move small helper functions to tlb-insns.c, Peter Maydell, 2024/12/13