Re: [PATCH 1/3] target/riscv: add a trap-misaligned-access property

[Alistair Francis]

On Thu, Dec 12, 2024 at 7:21 AM Frederic Konrad <fkonrad@amd.com> wrote:
>
> On riscv target, misaligned accesses are either authorized and implemented in
> hardware, or unimplemented and generate a trap to be implemented in software.
>
> At the moment misaligned accesses for rvi just succeed, the intention of this
> new property is to let the user choose to have a trap when a misaligned access
> happens.
>
> Signed-off-by: Frederic Konrad <fkonrad@amd.com>
> ---
>  target/riscv/cpu.c     | 5 +++++
>  target/riscv/cpu_cfg.h | 1 +
>  2 files changed, 6 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index f219f0c3b5..1696d3db2a 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2697,6 +2697,11 @@ static Property riscv_cpu_properties[] = {
>       * it with -x and default to 'false'.
>       */
>      DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false),
> +    /*
> +     * when set, misaligned accesses will generate a trap.
> +     */
> +    DEFINE_PROP_BOOL("trap-misaligned-access", RISCVCPU,
> +                     cfg.trap_misaligned_access, false),

This should be the last patch, we want to implement the feature before
we expose it.

Alistair