Re: [PATCH v4 1/3] hw/riscv: Support to load DTB after 3GB memory on 64-bit system.

[Jim Shu]

This is the correct fix, thanks!


On Tue, Dec 17, 2024 at 11:39 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Thu, Nov 21, 2024 at 1:41 AM Jim Shu <jim.shu@sifive.com> wrote:
> >
> > Larger initrd image will overlap the DTB at 3GB address. Since 64-bit
> > system doesn't have 32-bit addressable issue, we just load DTB to the end
> > of dram in 64-bit system.
> >
> > Signed-off-by: Jim Shu <jim.shu@sifive.com>
> > ---
> >  hw/riscv/boot.c            | 14 +++++++++-----
> >  hw/riscv/microchip_pfsoc.c |  4 ++--
> >  hw/riscv/sifive_u.c        |  4 ++--
> >  hw/riscv/spike.c           |  4 ++--
> >  hw/riscv/virt.c            |  2 +-
> >  include/hw/riscv/boot.h    |  2 +-
> >  6 files changed, 17 insertions(+), 13 deletions(-)
> >
> > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> > index 2e319168db..d36d3a7104 100644
> > --- a/hw/riscv/boot.c
> > +++ b/hw/riscv/boot.c
> > @@ -293,7 +293,7 @@ out:
> >   * The FDT is fdt_packed() during the calculation.
> >   */
> >  uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
> > -                                MachineState *ms)
> > +                                MachineState *ms, RISCVHartArrayState 
> > *harts)
> >  {
> >      int ret = fdt_pack(ms->fdt);
> >      hwaddr dram_end, temp;
> > @@ -317,11 +317,15 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, 
> > hwaddr dram_size,
> >
> >      /*
> >       * We should put fdt as far as possible to avoid kernel/initrd 
> > overwriting
> > -     * its content. But it should be addressable by 32 bit system as well.
> > -     * Thus, put it at an 2MB aligned address that less than fdt size from 
> > the
> > -     * end of dram or 3GB whichever is lesser.
> > +     * its content. But it should be addressable by 32 bit system as well 
> > in RV32.
> > +     * Thus, put it near to the end of dram in RV64, and put it near to 
> > the end
> > +     * of dram or 3GB whichever is lesser in RV32.
> >       */
> > -    temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
> > +    if (!riscv_is_32bit(harts)) {
> > +        temp = dram_end;
> > +    } else {
> > +        temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : 
> > dram_end;
> > +    }
> >
> >      return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
> >  }
> > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> > index f9a3b43d2e..ba8b0a2c26 100644
> > --- a/hw/riscv/microchip_pfsoc.c
> > +++ b/hw/riscv/microchip_pfsoc.c
> > @@ -519,7 +519,7 @@ static void 
> > microchip_icicle_kit_machine_init(MachineState *machine)
> >      bool kernel_as_payload = false;
> >      target_ulong firmware_end_addr, kernel_start_addr;
> >      uint64_t kernel_entry;
> > -    uint32_t fdt_load_addr;
> > +    uint64_t fdt_load_addr;
> >      DriveInfo *dinfo = drive_get(IF_SD, 0, 0);
> >
> >      /* Sanity check on RAM size */
> > @@ -625,7 +625,7 @@ static void 
> > microchip_icicle_kit_machine_init(MachineState *machine)
> >          /* Compute the fdt load address in dram */
> >          fdt_load_addr = 
> > riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
> >                                                 
> > memmap[MICROCHIP_PFSOC_DRAM_LO].size,
> > -                                               machine);
> > +                                               machine, &s->soc.u_cpus);
> >          riscv_load_fdt(fdt_load_addr, machine->fdt);
> >
> >          /* Load the reset vector */
> > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> > index c5e74126b1..05467e833a 100644
> > --- a/hw/riscv/sifive_u.c
> > +++ b/hw/riscv/sifive_u.c
> > @@ -519,7 +519,7 @@ static void sifive_u_machine_init(MachineState *machine)
> >      const char *firmware_name;
> >      uint32_t start_addr_hi32 = 0x00000000;
> >      int i;
> > -    uint32_t fdt_load_addr;
> > +    uint64_t fdt_load_addr;
> >      uint64_t kernel_entry;
> >      DriveInfo *dinfo;
> >      BlockBackend *blk;
> > @@ -606,7 +606,7 @@ static void sifive_u_machine_init(MachineState *machine)
> >
> >      fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base,
> >                                             memmap[SIFIVE_U_DEV_DRAM].size,
> > -                                           machine);
> > +                                           machine, &s->soc.u_cpus);
>
> This patch breaks boots with the sifive_u board.
>
> This diff fixes it, I'm going to squash the diff into this patch
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index ff6e26dec8..fd59124500 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -518,6 +518,7 @@ static void sifive_u_machine_init(MachineState *machine)
>     target_ulong firmware_end_addr, kernel_start_addr;
>     const char *firmware_name;
>     uint32_t start_addr_hi32 = 0x00000000;
> +    uint32_t fdt_load_addr_hi32 = 0x00000000;
>     int i;
>     uint64_t fdt_load_addr;
>     uint64_t kernel_entry;
> @@ -611,6 +612,7 @@ static void sifive_u_machine_init(MachineState *machine)
>
>     if (!riscv_is_32bit(&s->soc.u_cpus)) {
>         start_addr_hi32 = (uint64_t)start_addr >> 32;
> +        fdt_load_addr_hi32 = fdt_load_addr >> 32;
>     }
>
>     /* reset vector */
> @@ -625,7 +627,7 @@ static void sifive_u_machine_init(MachineState *machine)
>         start_addr,                    /* start: .dword */
>         start_addr_hi32,
>         fdt_load_addr,                 /* fdt_laddr: .dword */
> -        0x00000000,
> +        fdt_load_addr_hi32,
>         0x00000000,
>                                        /* fw_dyn: */
>     };