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Re: [PATCH v13 2/7] target/riscv: Add new CSR fields for S{sn, mn, m}pm
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v13 2/7] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0 |
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Date: |
Tue, 17 Dec 2024 15:32:19 +1000 |
On Mon, Dec 16, 2024 at 10:19 PM <baturo.alexey@gmail.com> wrote:
>
> From: Alexey Baturo <baturo.alexey@gmail.com>
>
> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
You shouldn't include a newline here
>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 8 ++++++++
> target/riscv/cpu_bits.h | 4 ++++
> target/riscv/cpu_cfg.h | 3 +++
> target/riscv/csr.c | 31 ++++++++++++++++++++++++++++++-
> target/riscv/pmp.c | 14 +++++++++++---
> target/riscv/pmp.h | 1 +
> 6 files changed, 57 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index e11264231d..417ff45544 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -128,6 +128,14 @@ typedef enum {
> EXT_STATUS_DIRTY,
> } RISCVExtStatus;
>
> +/* Enum holds PMM field values for Zjpm v1.0 extension */
> +typedef enum {
> + PMM_FIELD_DISABLED = 0,
> + PMM_FIELD_RESERVED = 1,
> + PMM_FIELD_PMLEN7 = 2,
> + PMM_FIELD_PMLEN16 = 3,
> +} RISCVPmPmm;
> +
> typedef struct riscv_cpu_implied_exts_rule {
> #ifndef CONFIG_USER_ONLY
> /*
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 2a6aff63ed..d8f9bc68e3 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -574,6 +574,7 @@ typedef enum {
> #define HSTATUS_VTW 0x00200000
> #define HSTATUS_VTSR 0x00400000
> #define HSTATUS_VSXL 0x300000000
> +#define HSTATUS_HUPMM 0x3000000000000
>
> #define HSTATUS32_WPRI 0xFF8FF87E
> #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
> @@ -734,6 +735,7 @@ typedef enum RISCVException {
> #define MENVCFG_CBIE (3UL << 4)
> #define MENVCFG_CBCFE BIT(6)
> #define MENVCFG_CBZE BIT(7)
> +#define MENVCFG_PMM (3ULL << 32)
> #define MENVCFG_ADUE (1ULL << 61)
> #define MENVCFG_PBMTE (1ULL << 62)
> #define MENVCFG_STCE (1ULL << 63)
> @@ -749,6 +751,7 @@ typedef enum RISCVException {
> #define SENVCFG_CBIE MENVCFG_CBIE
> #define SENVCFG_CBCFE MENVCFG_CBCFE
> #define SENVCFG_CBZE MENVCFG_CBZE
> +#define SENVCFG_PMM MENVCFG_PMM
>
> #define HENVCFG_FIOM MENVCFG_FIOM
> #define HENVCFG_LPE MENVCFG_LPE
> @@ -756,6 +759,7 @@ typedef enum RISCVException {
> #define HENVCFG_CBIE MENVCFG_CBIE
> #define HENVCFG_CBCFE MENVCFG_CBCFE
> #define HENVCFG_CBZE MENVCFG_CBZE
> +#define HENVCFG_PMM MENVCFG_PMM
> #define HENVCFG_ADUE MENVCFG_ADUE
> #define HENVCFG_PBMTE MENVCFG_PBMTE
> #define HENVCFG_STCE MENVCFG_STCE
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index 59d6fc445d..79a114eb07 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -128,6 +128,9 @@ struct RISCVCPUConfig {
> bool ext_ssaia;
> bool ext_sscofpmf;
> bool ext_smepmp;
> + bool ext_ssnpm;
> + bool ext_smnpm;
> + bool ext_smmpm;
> bool rvv_ta_all_1s;
> bool rvv_ma_all_1s;
> bool rvv_vl_half_avl;
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 941c9691da..5389ccb983 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -575,6 +575,9 @@ static RISCVException have_mseccfg(CPURISCVState *env,
> int csrno)
> if (riscv_cpu_cfg(env)->ext_zkr) {
> return RISCV_EXCP_NONE;
> }
> + if (riscv_cpu_cfg(env)->ext_smmpm) {
> + return RISCV_EXCP_NONE;
> + }
>
> return RISCV_EXCP_ILLEGAL_INST;
> }
> @@ -2379,6 +2382,12 @@ static RISCVException write_menvcfg(CPURISCVState
> *env, int csrno,
> if (env_archcpu(env)->cfg.ext_zicfiss) {
> mask |= MENVCFG_SSE;
> }
> +
> + /* Update PMM field only if the value is valid according to Zjpm
> v1.0 */
> + if (env_archcpu(env)->cfg.ext_smnpm &&
> + get_field(val, MENVCFG_PMM) != PMM_FIELD_RESERVED) {
> + mask |= MENVCFG_PMM;
> + }
> }
> env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
>
> @@ -2425,6 +2434,12 @@ static RISCVException write_senvcfg(CPURISCVState
> *env, int csrno,
> {
> uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE |
> SENVCFG_CBZE;
> RISCVException ret;
> + /* Update PMM field only if the value is valid according to Zjpm v1.0 */
> + if (env_archcpu(env)->cfg.ext_ssnpm &&
> + riscv_cpu_mxl(env) == MXL_RV64 &&
> + get_field(val, SENVCFG_PMM) != PMM_FIELD_RESERVED) {
> + mask |= SENVCFG_PMM;
> + }
>
> ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
> if (ret != RISCV_EXCP_NONE) {
> @@ -2489,6 +2504,12 @@ static RISCVException write_henvcfg(CPURISCVState
> *env, int csrno,
> get_field(env->menvcfg, MENVCFG_SSE)) {
> mask |= HENVCFG_SSE;
> }
> +
> + /* Update PMM field only if the value is valid according to Zjpm
> v1.0 */
> + if (env_archcpu(env)->cfg.ext_ssnpm &&
> + get_field(val, HENVCFG_PMM) != PMM_FIELD_RESERVED) {
> + mask |= HENVCFG_PMM;
> + }
> }
>
> env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
> @@ -3525,7 +3546,15 @@ static RISCVException read_hstatus(CPURISCVState *env,
> int csrno,
> static RISCVException write_hstatus(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> - env->hstatus = val;
> + uint64_t mask = (target_ulong)-1;
> + /* Update PMM field only if the value is valid according to Zjpm v1.0 */
> + if (!env_archcpu(env)->cfg.ext_ssnpm ||
> + riscv_cpu_mxl(env) != MXL_RV64 ||
> + get_field(val, HSTATUS_HUPMM) == PMM_FIELD_RESERVED) {
> + mask &= ~HSTATUS_HUPMM;
> + }
> + env->hstatus = (env->hstatus & ~mask) | (val & mask);
> +
> if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2)
> {
> qemu_log_mask(LOG_UNIMP,
> "QEMU does not support mixed HSXLEN options.");
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index a1b36664fc..a185c246d6 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -575,6 +575,13 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env,
> uint32_t addr_index)
> void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
> {
> int i;
> + uint64_t mask = MSECCFG_MMWP | MSECCFG_MML;
> + /* Update PMM field only if the value is valid according to Zjpm v1.0 */
> + if (riscv_cpu_cfg(env)->ext_smmpm &&
> + riscv_cpu_mxl(env) == MXL_RV64 &&
> + get_field(val, MSECCFG_PMM) != PMM_FIELD_RESERVED) {
> + mask |= MSECCFG_PMM;
> + }
>
> trace_mseccfg_csr_write(env->mhartid, val);
>
> @@ -590,12 +597,13 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong
> val)
>
> if (riscv_cpu_cfg(env)->ext_smepmp) {
> /* Sticky bits */
> - val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
> - if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) {
> + val |= (env->mseccfg & mask);
> + if ((val ^ env->mseccfg) & mask) {
> tlb_flush(env_cpu(env));
> }
> } else {
> - val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB);
> + mask |= MSECCFG_RLB;
> + val &= ~(mask);
> }
>
> /* M-mode forward cfi to be enabled if cfi extension is implemented */
> diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
> index e0530a17a3..271cf24169 100644
> --- a/target/riscv/pmp.h
> +++ b/target/riscv/pmp.h
> @@ -46,6 +46,7 @@ typedef enum {
> MSECCFG_USEED = 1 << 8,
> MSECCFG_SSEED = 1 << 9,
> MSECCFG_MLPE = 1 << 10,
> + MSECCFG_PMM = 3ULL << 32,
> } mseccfg_field_t;
>
> typedef struct {
> --
> 2.39.5
>
- [PATCH v13 0/7] Pointer Masking update for Zjpm v1.0, baturo . alexey, 2024/12/16
- [PATCH v13 2/7] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0, baturo . alexey, 2024/12/16
- Re: [PATCH v13 2/7] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0,
Alistair Francis <=
- [PATCH v13 3/7] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking, baturo . alexey, 2024/12/16
- [PATCH v13 5/7] target/riscv: Update address modify functions to take into account pointer masking, baturo . alexey, 2024/12/16
- [PATCH v13 6/7] target/riscv: Apply pointer masking for virtualized memory accesses, baturo . alexey, 2024/12/16
- [PATCH v13 4/7] target/riscv: Add pointer masking tb flags, baturo . alexey, 2024/12/16
- [PATCH v13 1/7] target/riscv: Remove obsolete pointer masking extension code., baturo . alexey, 2024/12/16