[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v10 1/7] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig
From: |
frank . chang |
Subject: |
[PATCH v10 1/7] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig |
Date: |
Tue, 17 Dec 2024 14:24:34 +0800 |
From: Tommy Wu <tommy.wu@sifive.com>
The boolean variable 'ext_smrnmi' is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index fe0c4173d2..28b43932db 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -129,6 +129,7 @@ struct RISCVCPUConfig {
bool ext_ssaia;
bool ext_sscofpmf;
bool ext_smepmp;
+ bool ext_smrnmi;
bool rvv_ta_all_1s;
bool rvv_ma_all_1s;
bool rvv_vl_half_avl;
--
2.34.1
- [PATCH v10 0/7] Add Smrnmi support, frank . chang, 2024/12/17
- [PATCH v10 2/7] target/riscv: Add Smrnmi CSRs, frank . chang, 2024/12/17
- [PATCH v10 4/7] target/riscv: Add Smrnmi mnret instruction, frank . chang, 2024/12/17
- [PATCH v10 7/7] target/riscv: Disable Smrnmi for the 'max' type CPU, frank . chang, 2024/12/17
- [PATCH v10 6/7] target/riscv: Add Zicfilp support for Smrnmi, frank . chang, 2024/12/17