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[PATCH v7 5/9] target/riscv: Add Ssdbltrp ISA extension enable switch
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From: |
Clément Léger |
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Subject: |
[PATCH v7 5/9] target/riscv: Add Ssdbltrp ISA extension enable switch |
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Date: |
Tue, 17 Dec 2024 10:07:01 +0100 |
Add the switch to enable the Ssdbltrp ISA extension.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cfb95eab14..c856a95593 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -199,6 +199,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11),
ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
+ ISA_EXT_DATA_ENTRY(ssdbltrp, PRIV_VERSION_1_13_0, ext_ssdbltrp),
ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen),
ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
@@ -1625,6 +1626,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false),
MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
MULTI_EXT_CFG_BOOL("ssaia", ext_ssaia, false),
+ MULTI_EXT_CFG_BOOL("ssdbltrp", ext_ssdbltrp, false),
MULTI_EXT_CFG_BOOL("svade", ext_svade, false),
MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
--
2.45.2
- [PATCH v7 0/9] target/riscv: Add support for Smdbltrp and Ssdbltrp extensions, Clément Léger, 2024/12/17
- [PATCH v7 1/9] target/riscv: Fix henvcfg potentially containing stale bits, Clément Léger, 2024/12/17
- [PATCH v7 3/9] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior, Clément Léger, 2024/12/17
- [PATCH v7 2/9] target/riscv: Add Ssdbltrp CSRs handling, Clément Léger, 2024/12/17
- [PATCH v7 5/9] target/riscv: Add Ssdbltrp ISA extension enable switch,
Clément Léger <=
- [PATCH v7 6/9] target/riscv: Add Smdbltrp CSRs handling, Clément Léger, 2024/12/17
- [PATCH v7 4/9] target/riscv: Implement Ssdbltrp exception handling, Clément Léger, 2024/12/17
- [PATCH v7 7/9] target/riscv: Implement Smdbltrp sret, mret and mnret behavior, Clément Léger, 2024/12/17
- [PATCH v7 9/9] target/riscv: Add Smdbltrp ISA extension enable switch, Clément Léger, 2024/12/17
- [PATCH v7 8/9] target/riscv: Implement Smdbltrp behavior, Clément Léger, 2024/12/17