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[PULL 15/19] target/arm: Add decodetree entry for DSB nXS variant
From: |
Peter Maydell |
Subject: |
[PULL 15/19] target/arm: Add decodetree entry for DSB nXS variant |
Date: |
Tue, 17 Dec 2024 17:19:33 +0000 |
From: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
The DSB nXS variant is always both a reads and writes request type.
Ignore the domain field like we do in plain DSB and perform a full
system barrier operation.
The DSB nXS variant is part of FEAT_XS made mandatory from Armv8.7.
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211144440.2700268-5-peter.maydell@linaro.org
[PMM: added missing "UNDEF unless feature present" check]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/a64.decode | 3 +++
target/arm/tcg/translate-a64.c | 9 +++++++++
2 files changed, 12 insertions(+)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 7aa10f51471..8c798cde2b4 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -260,6 +260,9 @@ WFIT 1101 0101 0000 0011 0001 0000 001 rd:5
CLREX 1101 0101 0000 0011 0011 ---- 010 11111
DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111
+# For the DSB nXS variant, types always equals MBReqTypes_All and we ignore the
+# domain bits.
+DSB_nXS 1101 0101 0000 0011 0011 -- 10 001 11111
ISB 1101 0101 0000 0011 0011 ---- 110 11111
SB 1101 0101 0000 0011 0011 0000 111 11111
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index ecbc46ba55f..7c65fc3a3b1 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -1986,6 +1986,15 @@ static bool trans_DSB_DMB(DisasContext *s, arg_DSB_DMB
*a)
return true;
}
+static bool trans_DSB_nXS(DisasContext *s, arg_DSB_nXS *a)
+{
+ if (!dc_isar_feature(aa64_xs, s)) {
+ return false;
+ }
+ tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
+ return true;
+}
+
static bool trans_ISB(DisasContext *s, arg_ISB *a)
{
/*
--
2.34.1
- [PULL 02/19] target/arm: Convert vfp_helper.c to fpst alias, (continued)
- [PULL 02/19] target/arm: Convert vfp_helper.c to fpst alias, Peter Maydell, 2024/12/17
- [PULL 01/19] target/arm: remove redundant code, Peter Maydell, 2024/12/17
- [PULL 07/19] target/arm: Convert sme_helper.c to fpst alias, Peter Maydell, 2024/12/17
- [PULL 05/19] target/arm: Convert neon_helper.c to fpst alias, Peter Maydell, 2024/12/17
- [PULL 04/19] target/arm: Convert vec_helper.c to fpst alias, Peter Maydell, 2024/12/17
- [PULL 06/19] target/arm: Convert sve_helper.c to fpst alias, Peter Maydell, 2024/12/17
- [PULL 09/19] target/arm: Convert neon_helper.c to use env alias, Peter Maydell, 2024/12/17
- [PULL 10/19] target/arm: Use float_status in helper_fcvtx_f64_to_f32, Peter Maydell, 2024/12/17
- [PULL 08/19] target/arm: Convert vec_helper.c to use env alias, Peter Maydell, 2024/12/17
- [PULL 11/19] target/arm: Use float_status in helper_vfp_fcvt{ds,sd}, Peter Maydell, 2024/12/17
- [PULL 15/19] target/arm: Add decodetree entry for DSB nXS variant,
Peter Maydell <=
- [PULL 18/19] hw/intc/arm_gicv3_its: Zero initialize local DTEntry etc structs, Peter Maydell, 2024/12/17
- [PULL 13/19] target/arm: Add ARM_CP_ADD_TLBI_NXS type flag for NXS insns, Peter Maydell, 2024/12/17
- [PULL 19/19] tests/functional: update sbsa-ref firmware used in test, Peter Maydell, 2024/12/17
- [PULL 14/19] target/arm: Add ARM_CP_ADD_TLBI_NXS type flag to TLBI insns, Peter Maydell, 2024/12/17
- [PULL 16/19] target/arm: Enable FEAT_XS for the max cpu, Peter Maydell, 2024/12/17
- [PULL 12/19] target/arm: Implement fine-grained-trap handling for FEAT_XS, Peter Maydell, 2024/12/17
- [PULL 17/19] tests/tcg/aarch64: add system test for FEAT_XS, Peter Maydell, 2024/12/17
- Re: [PULL 00/19] target-arm queue, Stefan Hajnoczi, 2024/12/19