Re: [PATCH for-10.0 3/9] target/riscv: add shcounterenw

[Daniel Henrique Barboza]

On 12/17/24 9:34 PM, Alistair Francis wrote:
> On Thu, Nov 14, 2024 at 3:20 AM Daniel Henrique Barboza
> <dbarboza@ventanamicro.com> wrote:
> > shcounterenw is defined in RVA22 as:
> >
> > "For any hpmcounter that is not read-only zero, the corresponding bit in
> > hcounteren must be writable."
> >
> > This is always true in TCG so let's claim support for it.
> >
> > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>
> This seems to break `make check`, specifically the
> `qtest-riscv64/bios-tables-test` test

In fact every patch that ended up adding a new riscv,isa that is always
enabled in rv64 will trigger a change in bios-tables-test. Figures.

I`ll re-send. Thanks,


Daniel

> Alistair
>
> > ---
> >   target/riscv/cpu.c | 1 +
> >   1 file changed, 1 insertion(+)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 4ad91722a0..6bfb1b1530 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -183,6 +183,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> >       ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
> >       ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
> >       ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
> > +    ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
> >       ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
> >       ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
> >       ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
> > --
> > 2.47.0