[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 41/41] rust: pl011: simplify handling of the FIFO enabled bit in L
From: |
Paolo Bonzini |
Subject: |
[PULL 41/41] rust: pl011: simplify handling of the FIFO enabled bit in LCR |
Date: |
Thu, 19 Dec 2024 09:32:28 +0100 |
Use ==/!= instead of going through bool and xor.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/hw/char/pl011/src/device.rs | 6 ++----
rust/hw/char/pl011/src/lib.rs | 6 ------
2 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs
index 4d620b442ed..18cc122951d 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -302,9 +302,7 @@ pub fn write(&mut self, offset: hwaddr, value: u64) {
Ok(LCR_H) => {
let new_val: registers::LineControl = value.into();
// Reset the FIFO state on FIFO enable or disable
- if bool::from(self.line_control.fifos_enabled())
- ^ bool::from(new_val.fifos_enabled())
- {
+ if self.line_control.fifos_enabled() !=
new_val.fifos_enabled() {
self.reset_rx_fifo();
self.reset_tx_fifo();
}
@@ -497,7 +495,7 @@ pub fn event(&mut self, event: QEMUChrEvent) {
#[inline]
pub fn fifo_enabled(&self) -> bool {
- matches!(self.line_control.fifos_enabled(), registers::Mode::FIFO)
+ self.line_control.fifos_enabled() == registers::Mode::FIFO
}
#[inline]
diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs
index 0747e130cae..69064d6929b 100644
--- a/rust/hw/char/pl011/src/lib.rs
+++ b/rust/hw/char/pl011/src/lib.rs
@@ -419,12 +419,6 @@ pub enum Mode {
FIFO = 1,
}
- impl From<Mode> for bool {
- fn from(val: Mode) -> Self {
- matches!(val, Mode::FIFO)
- }
- }
-
#[bitsize(2)]
#[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)]
/// `WLEN` Word length, field of [Line Control register](LineControl).
--
2.47.1
- [PULL 32/41] rust: qemu-api: add a module to wrap functions and zero-sized closures, (continued)
- [PULL 32/41] rust: qemu-api: add a module to wrap functions and zero-sized closures, Paolo Bonzini, 2024/12/19
- [PULL 33/41] kvm: consistently return 0/-errno from kvm_convert_memory, Paolo Bonzini, 2024/12/19
- [PULL 31/41] rust: qom: add initial subset of methods on Object, Paolo Bonzini, 2024/12/19
- [PULL 34/41] target/i386: Reset TSCs of parked vCPUs too on VM reset, Paolo Bonzini, 2024/12/19
- [PULL 35/41] rust: pl011: fix declaration of LineControl bits, Paolo Bonzini, 2024/12/19
- [PULL 36/41] rust: pl011: match break logic of C version, Paolo Bonzini, 2024/12/19
- [PULL 37/41] rust: pl011: always use reset() method on registers, Paolo Bonzini, 2024/12/19
- [PULL 38/41] rust: pl011: fix break errors and definition of Data struct, Paolo Bonzini, 2024/12/19
- [PULL 40/41] rust: pl011: fix migration stream, Paolo Bonzini, 2024/12/19
- [PULL 39/41] rust: pl011: extend registers to 32 bits, Paolo Bonzini, 2024/12/19
- [PULL 41/41] rust: pl011: simplify handling of the FIFO enabled bit in LCR,
Paolo Bonzini <=
- Re: [PULL 00/41] Rust, qdev, target/i386 changes for 2024-12-19, Richard Henderson, 2024/12/19